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BLM18SG121TN1D

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BLM18SG121TN1D
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Murata

Ferrite Chip, 1 Function(s), 3A, EIA STD PACKAGE SIZE 0603, 2 PIN

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    参考设计

    (5)
    RF Sampling 4-GSPS ADC Reference Design with 8-GHz DC-Coupled Differential Amplifier
    TIDA-00431: Wideband radio frequency (RF) receivers allow greatly increased flexibility in radio designs. The wide instantaneous bandwidth allows flexible tuning without changing hardware and the ability to capture multiple channels at widely separated frequencies. This reference design describes a wideband RF receiver utilizing a 4-GSPS analog-to-digital converter (ADC), with an 8-GHz, DC-coupled, fully differential amplifier front end. The amplifier front end provides signal gain and allows capture of signals down to DC, which is not possible with a balun-coupled input.
    Automotive 60W Brushless DC (BLDC) Motor Drive
    TIDA-00143: This TIDA-00143 reference design is a BLDC motor controller and is designed to operate from a single 12V (nominal) power supply which can vary over a wide range of voltages as found in typical automotive applications. The board is designed to drive motors in the 60W range, which require currents of 5 Amps. The size and layout of the board is intended to facilitate evaluation of the drive electronics and firmware, with easy access to key signals on individual test points. Connection to a wide variety of motors is possible using either the 3-contact connector or by soldering motor phase wires to plated-through holes in the board. The 12Vdc power is fused to prevent damage to the board or to bench power supplies in case of a motor fault during testing. Command and status of the motor can be communicated through the standard JTAG connector, or through PWM input and output signals. Users can also re-program the microcontroller through the JTAG connector, allowing customization to a wide variety of applications.
    Synchronization of JESD204B Giga-Sample ADCs using Xilinx Platform for Phased Array Radar Systems
    TIDA-00432: This system level design shows how two ADC12J4000 evaluation modules (EVMs) can be synchronized together using a Xilinx VC707 platform. The design document describes the required hardware modifications and device configurations, including the clocking scheme. Example configuration files are shown for each EVM. The FPGA firmware is described and the relevant Xilinx IP block configuration parameters are shown. Data taken on the actual hardware is shown and analyzed, showing synchronization within 50 ps without characterized cables or calibrated propagation delays.
    Schematic and Layout Recommendations for the Giga Sample Per Second (GSPS) ADC
    TIDA-00071: This reference design is a guide to the schematics and layout for the system designer using a GSPS ADC in their system. Use this reference design along with the datasheet — the datasheet is always the final authority. Also, the ADC1xDxxxx(RF)RB Reference Board provides a useful reference design. All design source files for the Reference Board as well as the CAD/CAE symbols for the ADC are available on the product web page or TI-Designs for download. For the purpose of this document, ADC or GSPS ADC refers to the ADC12D1800RF, ADC12D1600RF, ADC12D1000RF, ADC12D800RF, ADC12D500RF, ADC12D1800, ADC12D1600, ADC12D1000, ADC10D1500, ADC10D1000, ADC12D1600QML, and ADC10D1000QML.
    Clocking Solution Reference Design for GSPS ADCs
    TIDA-00359: Low cost, high performance clocking solution for GSPS data converters. This reference design discusses the use of a TRF3765, a low noise frequency synthesizer, generating the sampling clock for a 4 GSPS analog-to-digital converter (ADC12J4000). Experiments demonstrate data sheet comparable SNR and SFDR performance.
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