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ERJ-2RKF1000X

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ERJ-2RKF1000X
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Panasonic

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模型信息提供方: Samacsys
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参考设计

(16)
High Resolution, Portable Light Steering Reference Design using DLP Technology
DLP4500-C350REF: This reference design, featuring the DLP® 0.45” WXGA chipset and implemented in the DLP® LightCrafter™ 4500 evaluation module (EVM), enables flexible control of high resolution, accurate patterns for industrial, medical, and scientific applications. With a free USB-based GUI and API, developers can easily integrate TI’s innovative digital micromirror device (DMD) technology with cameras, sensors, motors, and other peripherals to create highly differentiated 3D machine vision systems, 3D printers, and augmented reality displays.
Altera Arria V GX FPGA Power Solution Reference Design
PMP9449: The PMP9449 reference design provides all the power supply rails necessary to power Altera's Arria® V GX family of FPGAs. It utilizes a TPS38600 to monitor the input supply and provide power on sequencing. This design features low cost, small footprint discrete ICs and is powered from a single 5V input.
High Efficiency, Power Density 1V/120A/30A/30A (4+1+1) w/ PMBus Reference Design for ASIC Processors
PMP11184.2: PMP11184 is a chipset solution for high current ASIC core rail regulation. It utilizes TPS53647 4-phase controller for 120A high current rail, which employs DCAP+ control for fast transient response and TI's proprietary AutoBalance for tight steady and dynamic phase-to-phase current balance. It also utilizes TPS40428 dual controller for dual 30A rails. Both controllers drive TI NexFET smart power stages for high power density and efficiency. PMBus capability and on-board NVM enable easy design, configuration, and customization, with telemetry of output voltage, current, temperature, and power.
Dual-channel XAUI to SFI Reference Design for Systems with Two or More SFP+ Optical Ports
TIDA-00234: The TIDA-00234 XAUI to SFI reference design is intended for Enterprise and Service Provider Networking applications like Ethernet Switches and Routers that implement multiple 10G Ethernet compliant Optical (SFP+) ports. This reference design features the TLK10232 device which is the most compact Dual-channel XAUI-to-SFI Transceiver with the lowest power consumption in its category. This reference design allows access to the high-speed signals (up to 10Gbps) generated by the TLK10232 via SMA connectors or an SFP+ Module via the SFP+ optical module cage. Also, featured is the CDCM6208 device that can provide extremely low-jitter Clock input to the TLK10232 in customer systems that do not have one available (or does not meet the jitter requirement of the system).
DisplayPort Video 4:1 Aggregation Reference Design
TIDA-00309: This verified reference design is a complete four channel DisplayPort aggregation and de-aggregation solution. One TLK10022 is used to aggregate four synchronous DisplayPort (DP) sources together into one 10.8 Gbps serial link. The serial data is transferred via copper or optical fiber where a second TLK10022 is used to de-aggregate and seamlessly redisplay the original video content.
Basestation Transceiver with DPD Feedback Path
TIDA-00068: The design is for a small cell base station development platform. It provides two real receive paths, two complex transmit paths, and a shared real feedback path. This design has macro basestation performance, but with small cell base station footprint. The current design handles up to 20MHz of bandwidth.
High Efficiency, Power Density 4-Phase 1V/120A PMBus Interface Reference Design for ASIC Processors
PMP11312: The PMP11312 reference design is a 4-phase PMBus converter for high current ASIC core rail regulation. It utilizes TPS53647 4-phase controller for 120A high current rail, which employs DCAP+ control for fast transient response and TI's proprietary AutoBalance for tight steady and dynamic phase-to-phase current balance. TPS53647 drives TI NexFET smart power stages for high power density and efficiency. Optimized layout and improved board stack-up (8-layer, 2oz-copper) achieve higher efficiency and higher power density. PMBus capability and on-board NVM enable easy design, configuration, and customization, with telemetry of output voltage, current, temperature, and power.
High efficiency scalable 3-phase 1V/90A PMBus power supply for ASIC core rails
PMP10962: The PMP10962 reference design is a 3-phase PMBus converter for high current ASIC core rail regulation. It employs DCAP+ control for fast transient response and TI's proprietary AutoBalance for tight steady and dynamic phase-to-phase current balance. It drives three TI NexFET smart power stages for high power density and efficiency. It easily scales-up/scales-down to meet a wide load range. PMBus capability and on-board NVM enable easy design, configuration, and customization, with telemetry of output voltage, current, temperature, and power.
Dual-Wideband RF-to-Digital Receiver Design
TIDA-00073: The TSW1265EVM is an example design of a wideband RF to digital dual receiver solution capable of digitizing up to 125MHz of spectrum. The system provides a reference on how to use the ADS4249, LMH6521, LMK0480x, and a dual mixer to achieve this. This reference EVEM coupled with a capture card such as the TSW1400 can be used to capture and analyze narrow band and wideband signals. Instructions are provided on how to change the LO and IF frequencies for different application needs. The TIDA-00073 was implemented with hardware from the TSW1265EVM.
1-GHz Bandwidth Dual Channel Transmitter up to 4-GHz Reference Design
TIDA-00409: The TSW38J84 EVM reference design provides a platform to demonstrate a wideband dual transmit solution that incorporates an integrated LO. The reference design utilizes the 2.5 GSPS DAC38J84 device with the high performance modulators: TRF3722 (including integrated PLL/VCO) and TRF3705. The TRF3722 and TRF3705 can be combined to form a dual transmit solution with the TRF3722 generating the local oscillator (LO) for both modulators. The interface between the DAC38J84 and the modulators is discussed as well as measurements showing the combined performance of the DAC and modulators. The measurements illustrate the bandwidth performance, output third order intercept performance, harmonic distortion and sideband suppression performance.
Schematic and Layout Recommendations for the Giga Sample Per Second (GSPS) ADC
TIDA-00071: This reference design is a guide to the schematics and layout for the system designer using a GSPS ADC in their system. Use this reference design along with the datasheet — the datasheet is always the final authority. Also, the ADC1xDxxxx(RF)RB Reference Board provides a useful reference design. All design source files for the Reference Board as well as the CAD/CAE symbols for the ADC are available on the product web page or TI-Designs for download. For the purpose of this document, ADC or GSPS ADC refers to the ADC12D1800RF, ADC12D1600RF, ADC12D1000RF, ADC12D800RF, ADC12D500RF, ADC12D1800, ADC12D1600, ADC12D1000, ADC10D1500, ADC10D1000, ADC12D1600QML, and ADC10D1000QML.
Wide-Bandwidth and High-Voltage Arbitrary Waveform Generator Front End
TIDA-00075: This design shows how to use an active interface with the current sink output of the DAC5682Z - typical applications for this include front ends for arbitrary waveform generators. The EVM includes the DAC5682Z for digital-to-analog conversion, an OPA695 to demonstrate an active interface implementation using a wide bandwidth operational amplifier and a THS3091 and THS3095 to showcase an operational amplifier with large voltage swing. Also included on board are a CDCM7005, VCXO and Reference for clock generation, and linear regulators for voltage regulation. Communication to the EVM is accomplished via a USB interface and GUI software.
Synchronizing Multiple JESD204B ADCs for Emitter Position Location Reference Design
TIDA-00467: A common technique to estimate the position of emitters uses the amplitude and phase shift data of a signal derived from an array of spatially distributed sensors. For such systems, it is important to guarantee a deterministic phase relationship between the sensors to minimize errors in the actual measured data. This application design will discuss how multiple Analog to Digital Converters (ADCs) with a JESD204B interface can be synchronized so that the sampled data from the ADCs are phase aligned.
JESD204B Link Latency Design Using a High Speed ADC
TIDA-00153: JESD204B links are the latest trend in data-converter digital interfaces. These links take advantage of high-speed serial-digital technology to offer many compelling benefits including improved channel densities. This reference design addresses one of the challenges of adopting the new interface: understanding and designing the link latency. An example achieves deterministic latency and determines the link latency of a system containing the Texas Instruments LM97937 ADC and Xilinx Kintex 7 FPGA.
Inductive Linear Position Sensing Booster Pack Reference Design
TIDA-00460: Typical implementations of distance measurements use expensive rare-earth magnets. To lower overall system cost, this reference design walks through the implementation of industry’s first inductance-to-digital converters from TI for linear position sensing without the use of any expensive rare-earth magnets. Linear position sensing determines the position of a target that moves laterally across an inductive sensor that is generating a magnetic field. An inductance-to-digital converter (LDC), like the LDC1000 or LDC1101, senses inductance changes of an inductor that comes into proximity with a conductive target, such as a piece of metal. The LDC measures this inductance shift to provide information about the position of a conductive target over a sensor coil. The inductance shift is caused by eddy currents generated in the target due to the magnetic field of the sensor. These eddy currents generate a secondary magnetic field that opposes the sensor field, causing a shift in the observed inductance.
Direct Down-Conversion System with I/Q Correction
TIDA-00078: The I/Q Correction block implemented in the Field Programmable Gate Array (FPGA) of the TSW6011EVM helps users to adopt a direct down conversion receiver architecture in a wireless system. The I/Q correction block consists of a single-tap blind algorithm, which corrects the frequency-independent I/Q imbalance in a complex zero-IF receiver system. Along with the I/Q correction block, the FPGA includes a digital gain block, a digital power-measurement block, x2 of interpolation block, an I/Q offset correction block, and a quadrature mixing block.
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