无法从文档中提取型号,请重试

Update your browser

Your browser (Internet Explorer) is out of date.

Update your browser for more security, comfort and the best experience for this site.

ERJ-3EKF1003V

加入BOM

ERJ-3EKF1003V
已加入BOM:

暂无描述

市场均价:
-
市场总库存:
-
生命周期状态: -
技术详情
替代料

CAD 模型信息

模型信息提供方: Samacsys
  • Part Symbol
  • Footprint
  • 3D Model
可下载的格式
  • Allegro
  • Altium
  • Cadence
  • CADSTAR
  • Circuit Studio
  • CR-5000
  • CR-8000
  • DesignSpark
  • DesignSpark PCB PRO
  • DipTrace
  • xDX Designer
  • Eagle
  • EasyEDA
  • Easy-PC
  • eCADSTAR
  • KiCad
  • Mentor
  • OrCAD
  • PADS
  • Proteus
  • Pulsonix
  • Quadcept
  • SOLIDWORKS PCB
  • TARGET 3001!
  • Zuken
  • 下载 CAD 档案

    从 Samacsys 下载 CAD 模型,即表示您同意我们的条款和隐私政策

    参考设计

    (6)
    Single Supply Analog Input Module Reference Design with 16-Bit, 8-Channel ADC for PLC
    TIPD166: This design is for a 16-bit, 8-channel analog input module for industrial programmable logic controller (PLC) systems. The circuit is realized with an 8-channel, 16-bit, successive-approximation-register (SAR), analog-to-digital converter (ADC) with an integrated precision reference and analog front-end (AFE) circuit.
    Basestation Transceiver with DPD Feedback Path
    TIDA-00068: The design is for a small cell base station development platform. It provides two real receive paths, two complex transmit paths, and a shared real feedback path. This design has macro basestation performance, but with small cell base station footprint. The current design handles up to 20MHz of bandwidth.
    Wide-Bandwidth and High-Voltage Arbitrary Waveform Generator Front End
    TIDA-00075: This design shows how to use an active interface with the current sink output of the DAC5682Z - typical applications for this include front ends for arbitrary waveform generators. The EVM includes the DAC5682Z for digital-to-analog conversion, an OPA695 to demonstrate an active interface implementation using a wide bandwidth operational amplifier and a THS3091 and THS3095 to showcase an operational amplifier with large voltage swing. Also included on board are a CDCM7005, VCXO and Reference for clock generation, and linear regulators for voltage regulation. Communication to the EVM is accomplished via a USB interface and GUI software.
    Synchronizing Multiple JESD204B ADCs for Emitter Position Location Reference Design
    TIDA-00467: A common technique to estimate the position of emitters uses the amplitude and phase shift data of a signal derived from an array of spatially distributed sensors. For such systems, it is important to guarantee a deterministic phase relationship between the sensors to minimize errors in the actual measured data. This application design will discuss how multiple Analog to Digital Converters (ADCs) with a JESD204B interface can be synchronized so that the sampled data from the ADCs are phase aligned.
    Direct Down-Conversion System with I/Q Correction
    TIDA-00078: The I/Q Correction block implemented in the Field Programmable Gate Array (FPGA) of the TSW6011EVM helps users to adopt a direct down conversion receiver architecture in a wireless system. The I/Q correction block consists of a single-tap blind algorithm, which corrects the frequency-independent I/Q imbalance in a complex zero-IF receiver system. Along with the I/Q correction block, the FPGA includes a digital gain block, a digital power-measurement block, x2 of interpolation block, an I/Q offset correction block, and a quadrature mixing block.
    新建BOM