GRM155R71H222KA01D中文资料_PDF数据手册

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muRata(村田)

Capacitor, Ceramic, Chip, General Purpose, 2200pF, 50V, ±10%, X7R, 0402 (1005 mm), 0.020"T, -55º ~ +125ºC, 7" Reel/Paper Tape

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详细参数

Source Content uid

GRM155R71H222KA01D

不含铅

符合

Active

0402

CHIP

Compliant

EAR99

10 weeks

0.7

0.0022 µF

CERAMIC CAPACITOR

CERAMIC

0.5 mm

1 mm

SURFACE MOUNT

YES

10%

125 °C

-55 °C

RECTANGULAR PACKAGE

SMT

10%

50 V

null

1005M/0402

YES

X7R

15% ppm/°C

WRAPAROUND

0.5 mm

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参考设计

(6)

Extending Rail-to-Rail Output Range for Fully Differential Amplifiers to Include True Zero Volts

TIDA-00187: Operational amplifiers (op amps) have been used for decades in signal conditioning circuits and measurement systems. An op amp that has an output spanning from negative to positive supply rail are generally referred to as rail-to-rail output (RRO) op amps. These devices have been used increasingly in portable systems to drive analog to digital converters (ADCs) where reducing power consumption while not sacrificing converter dynamic range is a key concern. While the task calls for the lowest power RRO op amps, circuit designers are finding out that rail-to-rail doesn’t exactly mean rail-to-rail. In reality the output is limited to a couple hundred millivolts within the rail depending on the loading. This problem is known as headroom and is the result of the RRO architecture. This application report focuses on using a low power RRO fully differential op amp (THS4531A) and low noise negative bias generator (LM7705) to achieve true zero volts in a ground referenced single supply system.

Basestation Transceiver with DPD Feedback Path

TIDA-00068: The design is for a small cell base station development platform. It provides two real receive paths, two complex transmit paths, and a shared real feedback path. This design has macro basestation performance, but with small cell base station footprint. The current design handles up to 20MHz of bandwidth.

Xilinx(r) Ultrascale(r) 16nm FPGA/SoC Power Solution for Mobile Radio Basestation with PMBus

PMP10555: The PMP10555 reference design provides all the power supply rails necessary to power Xilinx® Ultrascale® 16nm family of FPGAs/SoCs in a mobile radio basestation application. This design uses a PMBus compatible 20A integrated FET buck converter for the core and two multi-output buck regulator ICs to provide the remaining supplies necessary rails to power the FPGA. It also features two LM3880's for flexible power up and power down sequencing. This design uses a 12V input.

15A Non-Isolated DC/DC Converter

PMP4316: This reference design is 15A high density non-isolated DC/DC converter for telecom applications.

Xilinx Virtex Ultrascale FPGA Multi-Gigabit Transceiver (MGT) Power Reference Design with PMBus

PMP9408: The PMP9408 reference design provides all the power supply rails necessary to power the multi-gigabit transcievers (MGT) in Xilinx's Virtex® Ultrascale™ FPGAs. It utilizes a PMBus interface for current and voltage monitoring and meets Xilinx's low output voltage ripple requirement. This design uses a 5V input and offers a low cost discrete solution.

12Vin 1V 50A TPS40422 & Power Block II CSD87384 2 Phases w/PMBus Interface Reference Design

PMP8999: It is a two phase Synchronous Buck converter to provide high current with low ripple and fast dynamic response for high speed processor core applications. Same approach can also be used to power Memory and Input / Output power voltages, typically 1.2V to 3.3V. The two phase interleave reduces output ripple and allows faster response to rapidly changing loads. The two phases distribute power loss to eliminate need for added heat sink hardware. The "Project File" for the TPS40422 to communicate with TI's Fusion GUI is included. Output voltage and current limit can be adjusted and monitored thru the GUI. Additional settings can be accessed thru the same GUI. Test Report includes thermal images to show load capability, both with and without fan cooling. Testing done at 12Vin, where voltage stresses, losses and output ripple greatest. Design will work also at 5Vin with same high speed control loop, due to Input Voltage Feed Forward in the TPS40422.

< / 共 6 个参考设计 >

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GRM155R71H222KA01D

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GRM155R71H222KA01D

详细参数

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参考设计

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