参考设计
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TIDA-00254 Accurate Point Cloud Generation for 3D Machine Vision Applications using DLP® Technology | TI.com
TIDA-00254: The 3D Machine Vision reference design employs Texas Instruments DLP® Advanced Light Control Software Development Kit (SDK) for LightCrafter™ series controllers, which allows developers to easily construct 3D point clouds by integrating TI’s digital micromirror device (DMD) technology with cameras, sensors, motors or other peripherals. The highly differentiated 3D Machine Vision system utilizes the DLP® LightCrafter™ 4500 evaluation module (EVM), featuring the DLP4500 WXGA chipset, and enables flexible control of high resolution, accurate patterns for industrial, medical, and security applications.
High Resolution, Portable Light Steering Reference Design using DLP Technology
DLP4500-C350REF: This reference design, featuring the DLP® 0.45” WXGA chipset and implemented in the DLP® LightCrafter™ 4500 evaluation module (EVM), enables flexible control of high resolution, accurate patterns for industrial, medical, and scientific applications. With a free USB-based GUI and API, developers can easily integrate TI’s innovative digital micromirror device (DMD) technology with cameras, sensors, motors, and other peripherals to create highly differentiated 3D machine vision systems, 3D printers, and augmented reality displays.
DLP4500-C350REF High Resolution, Portable Light Steering Reference Design using DLP Technology | TI.com
DLP4500-C350REF: This reference design, featuring the DLP® 0.45” WXGA chipset and implemented in the DLP® LightCrafter™ 4500 evaluation module (EVM), enables flexible control of high resolution, accurate patterns for industrial, medical, and scientific applications. With a free USB-based GUI and API, developers can easily integrate TI’s innovative digital micromirror device (DMD) technology with cameras, sensors, motors, and other peripherals to create highly differentiated 3D machine vision systems, 3D printers, and augmented reality displays.
TIDEP0070 DDR ECC Reference Design to Improve Memory Reliability in 66AK2G02-based Systems | TI.com
TIDEP0070: The TIDEP0070 reference design describes system considerations for Dual Data Rate (DDR) memory interface with Error Correcting Code (ECC) support in high-reliability applications, based on the 66AK2G02 Multicore DSP + ARM processor System-on-Chip (SoC). It enables developers to implement a high reliability based solution rapidly by discussing system interfaces, board hardware, software, throughput performance and diagnostic procedures.
TIDEP0018 Parallel Camera Interface for Sitara Processors | TI.com
TIDEP0018: This camera interface design connects to a 10-bit parallel interface to the AM335x general purpose memory controller (GPMC) 16-bit multiplexed address/data bus. This design consumes roughly 150mW less power than typical USB solutions, and is ideal for applications like portable data terminals, ruggedized handhelds, portable consumer, industrial handhelds and others. The reference design is based on the QuickLogic 3.1 MP Camera Sensor (using an Aptina 3.1 MP sensor) connected to a camera expansion board. Together, they connect to the BeagleBone platform. The BeagleBone and the QuickLogic 3.1 MP camera add-on board are available for purchase. More information on QuickLogic: http://www.quicklogic.com More information about BeagleBone: http://www.ti.com/tool/beaglebn More information about the QuickLogic 3.1 MP camera add-on board for the BeagleBone, including design files and software: http://www.quicklogic.com/solutions/reference-designs/ti-sitara-beaglebone-camera-cape/
Reference Design using TMS320C6657 to Implement Efficient OPUS Codec Solution
TIDEP0036: The TIDEP0036 reference design provides an example of the ease of running TI optimized Opus encoder/decoder on the TMS320C6657 device. Since Opus supports a a wide range of bit rates, frame sizes and sampling rates, all with low delay, it has applicability for voice communications, networked audio and even high performance audio processing application. This design also highlights the performance improvements achieved when implementing the Opus codec on a DSP vs. a general purpose processor, like ARM. Depending upon the level of optimization of the code running on the genral purpose processor, implementing the Opus Codec on a C66x TI DSP core can have 3X the performance of an ARM CORTEX A-15 implementation. TMS320C66x DSPs support both audio and video codecs.
Parallel Camera Interface for Sitara Processors
TIDEP0018: This camera interface design connects to a 10-bit parallel interface to the AM335x general purpose memory controller (GPMC) 16-bit multiplexed address/data bus. This design consumes roughly 150mW less power than typical USB solutions, and is ideal for applications like portable data terminals, ruggedized handhelds, portable consumer, industrial handhelds and others. The reference design is based on the QuickLogic 3.1 MP Camera Sensor (using an Aptina 3.1 MP sensor) connected to a camera expansion board. Together, they connect to the BeagleBone platform. The BeagleBone and the QuickLogic 3.1 MP camera add-on board are available for purchase. More information on QuickLogic: http://www.quicklogic.com More information about BeagleBone: http://www.ti.com/tool/beaglebn More information about the QuickLogic 3.1 MP camera add-on board for the BeagleBone, including design files and software: http://www.quicklogic.com/solutions/reference-designs/ti-sitara-beaglebone-camera-cape/
TIDEP0054 Parallel Redundancy Protocol (PRP) Ethernet Reference Design for Substation Automation | TI.com
TIDEP0054: This TI Design implements a solution for high-reliability, low-latency network communications for substation automation equipment in Smart Grid transmission and distribution networks. It supports the Parallel Redundancy Protocol (PRP) specification in the IEC 62439 standard using the PRU-ICSS. This solution is a lower-cost alternative to FPGA approaches and provides the flexibility and performance to add features such as IEC 61850 support without additional components.
TIDEP0079 EtherCAT® Master Reference Design on Sitara AM57x Gb Ethernet and PRU-ICSS with Time Triggered Send | TI.com
TIDEP0079: The TIDEP0079 reference design demonstrates an EtherCAT® master interface running on the Sitara™ AM572x processor using the EC-Master stack from acontis. This EtherCAT master solution can be used for EtherCAT-based PLC or motion control applications. EtherCAT master is profiled on both the Ethernet switch and the PRU-ICSS Ethernet ports of the AM572x processor to give designers flexibility to use any of the two switch ports or four PRU-ICSS Ethernet ports on the device. The EtherCAT master implementation can achieve less than 100µs cycle times for both the switch and the PRU-ICSS Ethernet ports. Time-triggered send (TTS) can be enabled on the PRU-ICSS to reduce jitter, achieve shorter cycle times, and reduce latency in cases where distributed clocking is not used.
CC2531EM-IOT-HOME-GATEWAY-RD ZigBee Home Automation Gateway reference design | TI.com
CC2531EM-IOT-HOME-GATEWAY-RD: A gateway is a bridge that connects wireless devices to the Internet. This Linux-based Home Automation Gateway enables remote monitoring and control of ZigBee® powered nodes and devices inside the home. This gateway reference design includes ZigBee Home Automation (HA 1.2) certified software stack and tens of APIs that simplify ZigBee integration and application development in a Linux system.
TIDEP0050 EnDat 2.2 System Reference Design | TI.com
TIDEP0050: The TIDEP0050 TI Design implements the EnDat 2.2 Master protocol stack and hardware interface solution based on the HEIDENHAIN EnDat 2.2 standard for position or rotary encoders. The design is composed of the EnDat 2.2 Master protocol stack, half-duplex communications using RS485 transceivers and the line termination implemented on the Sitara AM437x Industrial Development Kit. This design is fully tested to meet the HEIDENHAIN EnDat 2.2 standard. Along with EnDat position feedback, the AM437x IDK is also able to support industrial communications and motor drive as described in the AM437x Single-Chip Motor-Control Design Guide.
TIDEP0043 Acontis EtherCAT Master Stack Reference Design | TI.com
TIDEP0043: The acontis EC-Master EtherCAT Master stack is a highly portable software stack that can be used on various embedded platforms. The EC-Master supports the high performance TI Sitara MPUs, it provides a sophisticated EtherCAT Master solution which customers can use to implement EtherCAT communication interface boards, EtherCAT based PLC or motion control applications. The EC-Master architectural design does not require additional tasks to be scheduled, thus the full stack functionality is available even on an OS less platform such as TI Starterware suported on AM335x. Due to this architecture combined with the high speed Ethernet driver it is possible to implement EtherCAT master based applications on the Sitara platform with short cycle times of 100 microseconds or even below.
8 Channel 1A/Ch High Side Driver for Programmable Logic Controller (PLC) Reference Design
TIDA-00183: The TIDA-00183 shows a high density, high power digital output circuitry with full protection and isolation for programmable logic controllers in factory automation and control environment. The BeagleBone-Black cape formfactor allows easy evaluation of the used driver chips and the interoperation with an MSP430 MCU for innovative protection schemes.
TIDEP0024 AM437x Low Power Suspend Mode with LPDDR2 | TI.com
TIDEP0024: This low power mode implementation realizes processor power consumption less than 0.1 mW while keeping LPDDR2 memory in self refresh consuming ~ 1.6 mW. The system solution is comprised of AM437x Sitara processor, LPDDR2 memory and TPS65218 power management IC and optimized for new low power mode along with support for legacy low power modes. The processor power is minimized by turning off all the processor power supplies except RTC power supply. System power state transitions including power supply control can be performed by single interface signal (PMIC_PWR_EN signal) with PMIC register programming.
TIDEP0025 Single Chip Drive for Industrial Communications and Motor Control | TI.com
TIDEP0025: This TI design implements a hardware interface solution based on the HEIDENHAIN EnDat 2.2 standard for position or rotary encoders. The platform also allows designers to implement real-time EtherCAT communications standards in a broad range of industrial automation equipment. It enables designers with a low foot print, low power and single chip solution in applications such as industrial automation, factory automation or industrial communication.
Single Chip Drive for Industrial Communications and Motor Control
TIDEP0025: This TI design implements a hardware interface solution based on the HEIDENHAIN EnDat 2.2 standard for position or rotary encoders. The platform also allows designers to implement real-time EtherCAT communications standards in a broad range of industrial automation equipment. It enables designers with a low foot print, low power and single chip solution in applications such as industrial automation, factory automation or industrial communication.
EnDat 2.2 System Reference Design
TIDEP0050: The TIDEP0050 TI Design implements the EnDat 2.2 Master protocol stack and hardware interface solution based on the HEIDENHAIN EnDat 2.2 standard for position or rotary encoders. The design is composed of the EnDat 2.2 Master protocol stack, half-duplex communications using RS485 transceivers and the line termination implemented on the Sitara AM437x Industrial Development Kit. This design is fully tested to meet the HEIDENHAIN EnDat 2.2 standard. Along with EnDat position feedback, the AM437x IDK is also able to support industrial communications and motor drive as described in the AM437x Single-Chip Motor-Control Design Guide.
TIDEP0067 66AK2G02 DSP + ARM Processor Power Solution Reference Design | TI.com
TIDEP0067: The TIDEP0067 TI Reference Design is based on the 66AK2G02 multicore System-on-Chip (SoC) processor and companion TPS659118 power management integrated circuit (PMIC) which includes power supplies and power sequencing for the 66AK2G02 processor in a single device. This power solution design also includes the first stage buck converters to support a 12 V input and the DDR termination regulator for DDR3L memory. The reference design is tested and includes hardware reference (EVM), software (Processor SDK) and test data.
TIDEP0069 66AK2G02 DSP + ARM Processor Audio Processing Reference Design | TI.com
TIDEP0069: The TIDEP0069 TI Reference Design is a reference platform based on the 66AK2G02 DSP + ARM processor System-On-Chip (SoC) and companion AIC3106 Audio codec and enables a quick path to audio processing algorithm design and demonstration. This audio solution design includes real time application software using the Processor SDK TI RTOS software that demonstrates audio processing block on the DSP to add audio effects.
TIDEP0036 Reference Design using TMS320C6657 to Implement Efficient OPUS Codec Solution | TI.com
TIDEP0036: The TIDEP0036 reference design provides an example of the ease of running TI optimized Opus encoder/decoder on the TMS320C6657 device. Since Opus supports a a wide range of bit rates, frame sizes and sampling rates, all with low delay, it has applicability for voice communications, networked audio and even high performance audio processing application. This design also highlights the performance improvements achieved when implementing the Opus codec on a DSP vs. a general purpose processor, like ARM. Depending upon the level of optimization of the code running on the genral purpose processor, implementing the Opus Codec on a C66x TI DSP core can have 3X the performance of an ARM CORTEX A-15 implementation. TMS320C66x DSPs support both audio and video codecs.
TIDEP0068 PCI Express PCB Design Considerations Reference Design for the 66AK2G02 General Purpose EVM 'GP EVM' | TI.com
TIDEP0068: PCI-Express provides for low pin-count, high reliability, and high-speed with data transfer at rates of up to 5.0 Gbps per lane, per direction, and an PCIe module is included on the TI 66AK2G02 DSP + ARM Processor system on chip (SoC). This PCIe PCB design considerations reference design helps developers optimize the printed circuit board (PCB) design by providing best-practice PCB for the PCIe portion of the 66AK2G02 Processor SoC. This in turn enables developers achieve desired PCIe signal performance on the first PCB implementation pass, allowing rapid focus on K2G Processor based application development and test. The 66AK2G02 General Purpose EVM (EVMK2G) is used as a reference to discuss some of these considerations.
AM437x Low Power Suspend Mode with LPDDR2
TIDEP0024: This low power mode implementation realizes processor power consumption less than 0.1 mW while keeping LPDDR2 memory in self refresh consuming ~ 1.6 mW. The system solution is comprised of AM437x Sitara processor, LPDDR2 memory and TPS65218 power management IC and optimized for new low power mode along with support for legacy low power modes. The processor power is minimized by turning off all the processor power supplies except RTC power supply. System power state transitions including power supply control can be performed by single interface signal (PMIC_PWR_EN signal) with PMIC register programming.
TIDM-DELFINO-ETHERCAT EtherCAT Interface for High Performance MCU Reference Design | TI.com
TIDM-DELFINO-ETHERCAT: This reference design demonstrates how to connect a C2000 Delfino MCU to an EtherCAT™ ET1100 slave controller. The interface supports both demultiplexed address/data busses for maximum bandwidth and minimum latency and a SPI mode for low pin-count EtherCAT communication. The slave controller offloads the processing of 100Mbps Ethernet-based fieldbus communication, thereby eliminating CPU overhead for these tasks.
Accurate Point Cloud Generation for 3D Machine Vision Applications using DLP® Technology
TIDA-00254: The 3D Machine Vision reference design employs Texas Instruments DLP Software Development Kit (SDK) allowing developers to easily construct 3D point clouds by integrating TI’s digital micromirror device (DMD) technology with cameras, sensors, motors or other peripherals. The highly differentiated 3D Machine Vision systems utilizes the DLP® LightCrafter™ 4500 evaluation module (EVM), featuring the DLP® 0.45” WXGA chipset, and enables flexible control of high resolution, accurate patterns for industrial, medical, and security applications.
ZigBee Home Automation Gateway reference design
CC2531EM-IOT-HOME-GATEWAY-RD: A gateway is a bridge that connects wireless devices to the Internet. This Linux-based Home Automation Gateway enables remote monitoring and control of ZigBee® powered nodes and devices inside the home. This gateway reference design includes ZigBee Home Automation (HA 1.2) certified software stack and tens of APIs that simplify ZigBee integration and application development in a Linux system.
Acontis EtherCAT Master Stack Reference Design
TIDEP0043: The acontis EC-Master EtherCAT Master stack is a highly portable software stack that can be used on various embedded platforms. The EC-Master supports the high performane TI Sitara MPUs, it provides a sophisticated EtherCAT Master solution which customers can use to implement EtherCAT communication interface boards, EtherCAT based PLC or motion control applications. The EC-Master architectural design does not require additional tasks to be scheduled, thus the full stack functionality is available even on an OS less platform such as TI Starterware suported on AM335x. Due to this architecture combined with the high speed Ethernet driver it is possible to implement EtherCAT master based applications on the Sitara platform with short cycle times of 100 microseconds or even below.
TIDEP0078 OPC UA Data Access Server for AM572x Reference Design | TI.com
TIDEP0078: OPC UA is an industrial machine-to-machine protocol designed to allow interoperability and communication between all machines connected under Industry 4.0. The TIDEP0078 TI Design demonstrates use of the MatrikonOPC™ OPC UA server development kit (SDK) to allow communications using an OPC UA data access (DA) server running embedded in a project or design. The OPC UA DA deals with real-time data and is best suited for industrial automation applications where time is an important aspect of the data. A reference OPC UA server implementation is provided that accesses the GPIO capabilities of the AM572x IDK. The reference code can be extended to provide an OPC UA interface to any data the AM572x IDK board can access including data acquired through Profibus, RS-485, CAN bus, and industrial Ethernet-based protocols such as EtherCAT™ or PROFINET™ using the Programmable Real-time Unit Industrial Communication Subsystems (PRU-ICSS).
TIDEP0074 Packet Processing Engine Reference Design for IEC61850 GOOSE Forwarding | TI.com
TIDEP0074: The TIDEP0074 reference design demonstrates packet switching and filtering logic implemented in the M4 core of AM572x based upon the Ethertype, MAC address and Application ID (APPID) of GOOSE packets received from the PRU-ICSS. Packets are filtered and routed to destinations in order to allow the time-critical events defined in substation communication standard IEC 61580 to be serviced in a dedicated core. The design additionally shows multi-core communication between the ARM Cortex™-A15, Cortex™-M4 and DSP C66x™ cores of the AM572x while Linux runs on the A15s and TI-RTOS runs on the M4 and DSP cores.
