参考设计
(47)
Ethernet Powerlink Development Platform Reference Design
TIDEP0028: The TIDEP0028 Ethernet Powerlink development platform combines the AM335x Sitara processor family from Texas Instruments (TI) and the Powerlink open media access control (MAC) layer into a single system-on-chip (SoC) solution. Targeted for Ethernet Powerlink slave communications, the TIDEP0028 allows designers to implement the real-time Powerlink communication standard for a broad range of industrial automation equipment. The design is based on the TMDSICE3359 Industrial Communications Engine (ICE).
Power and Thermal Design Considerations Using TI's AM57x Processor Reference Design
TIDEP0047: This TI Design (TIDEP0047) is a reference platform based on the AM57x processor and companion TPS659037 power management integrated circuit (PMIC). This TI Design specifically highlights important power and thermal design considerations and techniques for systems designed with AM57x and TPS659037. It includes reference material and documentation covering power management design, power distribution network (PDN) design considerations, thermal design considerations, estimating power consumption, and a power consumption summary.
Ethernet/IP Communications Development Platform
TIDEP0003: Targeted for Ethernet/IP slave communications, this development platform allows designers to mplement Ethernet/IP communications standards in a broad range of industrial automation equipment. It enables low foot print designs in applications such as industrial automation, factory automation or industrial communication with minimal external components and with best in class low power performance.
TIDEP0032 Multi-Protocol Industrial Ethernet Detection w/PRU-ICSS for Industrial Automation Reference Design | TI.com
TIDEP0032: Industrial Ethernet for Industrial Automation exist in more than 30 industrial standards. Some of the well-established real-time Ethernet protocols, like EtherCAT, EtherNet/IP, PROFINET, Sercos III and PowerLink require dedicated MAC hardware support in terms of FPGA or ASICs. The Programmable Real-time Unit inside the Industrial Communication Subsystem (PRU-ICSS), which exists as HW block inside the Sitara processors family, replaces FPGA or ASICS by a single chip solution. A firmware in the PRU-ICSS allows detecting the type of Industrial Ethernet protocol and loading the appropriate industrial application during run-time into Sitara processor. This TI Design describes the multi-protocol Industrial Ethernet protocol detection firmware for PRU-ICSS.
TIDEP0008 PROFINET Communications Development Platform | TI.com
TIDEP0008: Targeted for PROFINET slave communications, this development platform allows designers to implement PROFINET communications standards in a broad range of industrial automation equipment. It enables low foot print designs in applications such as industrial automation, factory automation or industrial communication with minimal external components and with best in class low power performance.
Data Concentrator Reference Design
TIDEP0006: The data concentrator reference design gives developers the ultimate level of flexibility and scalability with numerous performance, cost and connectivity options for their data concentrator designs. It includes advanced hardware and software that reduce development time by up to nine months while still supporting connectivity to more than 1,000 smart meters. Developers can easily plug in different connectivity modules, including Sub-1GHz (LPRF), general packet radio service (GPRS), near field communication (NFC) and TI's power line communication (PLC) system-on-module robust G3 and PRIME support.
TIDEP0047 Power and Thermal Design Considerations Using TI's AM57x Processor Reference Design | TI.com
TIDEP0047: This TI Design (TIDEP0047) is a reference platform based on the AM57x processor and companion TPS659037 power management integrated circuit (PMIC). This TI Design specifically highlights important power and thermal design considerations and techniques for systems designed with AM57x and TPS659037. It includes reference material and documentation covering power management design, power distribution network (PDN) design considerations, thermal design considerations, estimating power consumption, and a power consumption summary.
TIDEP0070 DDR ECC Reference Design to Improve Memory Reliability in 66AK2G02-based Systems | TI.com
TIDEP0070: The TIDEP0070 reference design describes system considerations for Dual Data Rate (DDR) memory interface with Error Correcting Code (ECC) support in high-reliability applications, based on the 66AK2G02 Multicore DSP + ARM processor System-on-Chip (SoC). It enables developers to implement a high reliability based solution rapidly by discussing system interfaces, board hardware, software, throughput performance and diagnostic procedures.
Reference Design using TMS320C6657 to Implement Efficient OPUS Codec Solution
TIDEP0036: The TIDEP0036 reference design provides an example of the ease of running TI optimized Opus encoder/decoder on the TMS320C6657 device. Since Opus supports a a wide range of bit rates, frame sizes and sampling rates, all with low delay, it has applicability for voice communications, networked audio and even high performance audio processing application. This design also highlights the performance improvements achieved when implementing the Opus codec on a DSP vs. a general purpose processor, like ARM. Depending upon the level of optimization of the code running on the genral purpose processor, implementing the Opus Codec on a C66x TI DSP core can have 3X the performance of an ARM CORTEX A-15 implementation. TMS320C66x DSPs support both audio and video codecs.
TIDEP0028 Ethernet Powerlink Development Platform Reference Design | TI.com
TIDEP0028: The TIDEP0028 Ethernet Powerlink development platform combines the AM335x Sitara processor family from Texas Instruments (TI) and the Powerlink open media access control (MAC) layer into a single system-on-chip (SoC) solution. Targeted for Ethernet Powerlink slave communications, the TIDEP0028 allows designers to implement the real-time Powerlink communication standard for a broad range of industrial automation equipment. The design is based on the TMDSICE3359 Industrial Communications Engine (ICE).
Multi-Protocol Industrial Ethernet Detection w/PRU-ICSS for Industrial Automation Reference Design
TIDEP0032: Industrial Ethernet for Industrial Automation exist in more than 30 industrial standards. Some of the well-established real-time Ethernet protocols, like EtherCAT, EtherNet/IP, PROFINET, Sercos III and PowerLink require dedicated MAC hardware support in terms of FPGA or ASICs. The Programmable Real-time Unit inside the Industrial Communication Subsystem (PRU-ICSS), which exists as HW block inside the Sitara processors family, replaces FPGA or ASICS by a single chip solution. A firmware in the PRU-ICSS allows detecting the type of Industrial Ethernet protocol and loading the appropriate industrial application during run-time into Sitara processor. This TI Design describes the multi-protocol Industrial Ethernet protocol detection firmware for PRU-ICSS.
TIDEP0054 Parallel Redundancy Protocol (PRP) Ethernet Reference Design for Substation Automation | TI.com
TIDEP0054: This TI Design implements a solution for high-reliability, low-latency network communications for substation automation equipment in Smart Grid transmission and distribution networks. It supports the Parallel Redundancy Protocol (PRP) specification in the IEC 62439 standard using the PRU-ICSS. This solution is a lower-cost alternative to FPGA approaches and provides the flexibility and performance to add features such as IEC 61850 support without additional components.
TIDA-01065 Isolated Self-Powered AC Solid State Relay with MOSFETs Reference Design | TI.com
TIDA-01065: The isolated self-powered AC solid state relay with MOSFETs reference design is a relay replacement that enables efficient power management for a low-power alternative to standard electromechanical relays. The galvanic isolation is implemented capacitively, creating a cost-efficient, reduced footprint solution for multiple relay replacement in thermostats and other similar equipment.
TIDEP0006 Data Concentrator Reference Design | TI.com
TIDEP0006: The data concentrator reference design gives developers the ultimate level of flexibility and scalability with numerous performance, cost and connectivity options for their data concentrator designs. It includes advanced hardware and software that reduce development time by up to nine months while still supporting connectivity to more than 1,000 smart meters. Developers can easily plug in different connectivity modules, including Sub-1GHz (LPRF), general packet radio service (GPRS), near field communication (NFC) and TI's power line communication (PLC) system-on-module robust G3 and PRIME support.
TIDEP0050 EnDat 2.2 System Reference Design | TI.com
TIDEP0050: The TIDEP0050 TI Design implements the EnDat 2.2 Master protocol stack and hardware interface solution based on the HEIDENHAIN EnDat 2.2 standard for position or rotary encoders. The design is composed of the EnDat 2.2 Master protocol stack, half-duplex communications using RS485 transceivers and the line termination implemented on the Sitara AM437x Industrial Development Kit. This design is fully tested to meet the HEIDENHAIN EnDat 2.2 standard. Along with EnDat position feedback, the AM437x IDK is also able to support industrial communications and motor drive as described in the AM437x Single-Chip Motor-Control Design Guide.
TIDA-00352 SDI Video Aggregation Reference Design | TI.com
TIDA-00352: This verified reference design is a complete four channel SDI aggregation and de-aggregation solution. One TLK10022 is used to aggregate four synchronous HD-SDI sources together into one 5.94 Gbps serial link. The serial data is transferred via copper or optical fiber where a second TLK10022 is used to de-aggregate and seamlessly redisplay the original video content.
DisplayPort Video 4:1 Aggregation Reference Design
TIDA-00309: This verified reference design is a complete four channel DisplayPort aggregation and de-aggregation solution. One TLK10022 is used to aggregate four synchronous DisplayPort (DP) sources together into one 10.8 Gbps serial link. The serial data is transferred via copper or optical fiber where a second TLK10022 is used to de-aggregate and seamlessly redisplay the original video content.
TIDEP0033 SPI Master with Signal Path Delay Compensation Reference Design | TI.com
TIDEP0033: The Programmable Real-time unit within the Industrial Communication Subsystem (PRU-ICSS) enables customers to support real-time critical applications without using FPGAs, CPLDs or ASICs. This TI design describes the implementation of the SPI master protocol with signal path delay compensation on PRU-ICSS. It supports the 32-bit communication protocol of ADS8688 with a SPI clock frequency of up to 16.7MHz.
EtherCAT Communications Development Platform
TIDEP0001: Targeted for EtherCAT slave communications, this development platform allows designers to implement real-time EtherCAT communications standards in a broad range of industrial automation equipment. It enables low foot print designs in applications such as industrial automation, factory automation or industrial communication with minimal external components and with best in class low power performance.
TIDA-01226 Compact Full HD 1080p (up to 16 Amps) Projection Display Reference Design Using DLP Pico Technology | TI.com
TIDA-01226: This reference design, featuring the DLP Pico™ 0.47-inch TRP Full-HD 1080p display chipset and implemented in the DLP LightCrafter Display 4710 G2 evaluation module (EVM), enables use of full HD resolution for projection display applications such as accessory projectors, screenless displays, interactive displays, wearables (including head mounted displays), signage, industrial and medical displays. The chipset used in the design is comprised of the DLP4710 (.47 1080p) DMD, the DLPC3439 display controller and the DLPA3005 PMIC/LED driver.
TIDEP0059 G3-PLC (CENELEC Band) Data Concentrator Reference Design | TI.com
TIDEP0059: The TIDEP0059 reference design implements a complete Power Line Communications (PLC) Data Concentrator based upon the G3-PLC industry standard. It operates in the 36 kHz – 91 kHz band defined by the CENELEC for Smart Grid communications. The reference design includes G3-PLC software which supports the management of up to 1000 G3-PLC end points in a neighborhood area network. The reference design supports the full 312 Kbps data throughput specified by the G3-PLC standard.
PROFINET Communications Development Platform
TIDEP0008: Targeted for PROFINET slave communications, this development platform allows designers to implement PROFINET communications standards in a broad range of industrial automation equipment. It enables low foot print designs in applications such as industrial automation, factory automation or industrial communication with minimal external components and with best in class low power performance.
TIDEP0025 Single Chip Drive for Industrial Communications and Motor Control | TI.com
TIDEP0025: This TI design implements a hardware interface solution based on the HEIDENHAIN EnDat 2.2 standard for position or rotary encoders. The platform also allows designers to implement real-time EtherCAT communications standards in a broad range of industrial automation equipment. It enables designers with a low foot print, low power and single chip solution in applications such as industrial automation, factory automation or industrial communication.
TIDEP0010 Sercos III Communications Development Platform | TI.com
TIDEP0010: The TIDEP0010 Sercos III communication development platform combines the AM335x Sitara processor family from Texas Instruments (TI) and the Sercos III media access control (MAC) layer into a single system-on-chip (SoC) solution. Targeted for Sercos III slave communications, the TIDEP0010 allows designers to implement the real-time Sercos III communication standard for a broad range of industrial automation equipment. The design is based on the TMDSICE3359 Industrial Communications Engine (ICE).
TIDA-01037 20-bit, 1-MSPS Isolator Optimized Data Acquisition Reference Design Maximizing SNR and Sample Rate | TI.com
TIDA-01037: TIDA-01037 is a 20-bit, 1 MSPS isolated analog input data acquisition reference design that utilizes two different isolator devices to maximize signal chain SNR and sample rate performance. For signals requiring low jitter, such as ADC sampling clocks, TI’s ISO73xx family of low jitter devices are used whereas TI’s high speed ISO78xx family of devices are used to maximize data sample rate. By combing these two isolator solutions, high frequency performance is significantly improved by minimizing sample clock jitter across the isolation boundary, and data throughput is improved by maximizing isolator signaling rate. Additional improvements are realized by utilizing TI’s advanced ADC multiSPITM and source-synchronous features. Finally, all key design theories are described and measured results presented.
TIDEP0058 G3-PLC (FCC Band) Data Concentrator Reference Design | TI.com
TIDEP0058: The TIDEP0058 reference design implements a complete Power Line Communications (PLC) Data Concentrator based upon the G3-PLC industry standard. It operates in the 157 kHz – 487 kHz band defined by the FCC for Smart Grid communications. The reference design includes G3-PLC software which supports the management of up to 1000 G3-PLC end points in a neighborhood area network. The reference design supports the full 312 Kbps data throughput specified by the G3-PLC standard.
Single Chip Drive for Industrial Communications and Motor Control
TIDEP0025: This TI design implements a hardware interface solution based on the HEIDENHAIN EnDat 2.2 standard for position or rotary encoders. The platform also allows designers to implement real-time EtherCAT communications standards in a broad range of industrial automation equipment. It enables designers with a low foot print, low power and single chip solution in applications such as industrial automation, factory automation or industrial communication.
TIDEP0046 Monte-Carlo Simulation on AM57x Using OpenCL for DSP Acceleration Reference Design | TI.com
TIDEP0046: TI’s high performance ARM® Cortex®-A15 based AM57x processors also integrate C66x DSPs. These DSPs were designed to handle high signal and data processing tasks that are often required by industrial, automotive and financial applications. The AM57x OpenCL implementation makes it easy for users to utilize DSP acceleration for high computational tasks while using a standard programming model and language, thereby removing the need for deep knowledge of the DSP architecture. The TIDEP0046 TI reference design provides an example of using DSP acceleration to generate a very long sequence of normal random numbers using standard C/C++ code.
TIDEP0001 EtherCAT Communications Development Platform | TI.com
TIDEP0001: Targeted for EtherCAT slave communications, this development platform allows designers to implement real-time EtherCAT communications standards in a broad range of industrial automation equipment. It enables low foot print designs in applications such as industrial automation, factory automation or industrial communication with minimal external components and with best in class low power performance.
SPI Master with Signal Path Delay Compensation Reference Design
TIDEP0033: The Programmable Real-time unit within the Industrial Communication Subsystem (PRU-ICSS) enables customers to support real-time critical applications without using FPGAs, CPLDs or ASICs. This TI design describes the implementation of the SPI master protocol with signal path delay compensation on PRU-ICSS. It supports the 32-bit communication protocol of ADS8688 with a SPI clock frequency of up to 16.7MHz.
EnDat 2.2 System Reference Design
TIDEP0050: The TIDEP0050 TI Design implements the EnDat 2.2 Master protocol stack and hardware interface solution based on the HEIDENHAIN EnDat 2.2 standard for position or rotary encoders. The design is composed of the EnDat 2.2 Master protocol stack, half-duplex communications using RS485 transceivers and the line termination implemented on the Sitara AM437x Industrial Development Kit. This design is fully tested to meet the HEIDENHAIN EnDat 2.2 standard. Along with EnDat position feedback, the AM437x IDK is also able to support industrial communications and motor drive as described in the AM437x Single-Chip Motor-Control Design Guide.
TIDEP0003 Ethernet/IP Communications Development Platform | TI.com
TIDEP0003: Targeted for Ethernet/IP slave communications, this development platform allows designers to mplement Ethernet/IP communications standards in a broad range of industrial automation equipment. It enables low foot print designs in applications such as industrial automation, factory automation or industrial communication with minimal external components and with best in class low power performance.
TIDEP0067 66AK2G02 DSP + ARM Processor Power Solution Reference Design | TI.com
TIDEP0067: The TIDEP0067 TI Reference Design is based on the 66AK2G02 multicore System-on-Chip (SoC) processor and companion TPS659118 power management integrated circuit (PMIC) which includes power supplies and power sequencing for the 66AK2G02 processor in a single device. This power solution design also includes the first stage buck converters to support a 12 V input and the DDR termination regulator for DDR3L memory. The reference design is tested and includes hardware reference (EVM), software (Processor SDK) and test data.
TIDA-00663 LIDAR Pulsed Time of Flight Reference Design | TI.com
TIDA-00663: Light Detection and Ranging (LIDAR) systems use the time taken by the light to fly back and forth to an object in an effort to measure the distance to this target. The TIDA-00663 reference design shows how to design the time measurement back-end for LIDAR based on Time to Digital Converter (TDC) as well as associated front-end. The LIDAR pulsed time of flight reference design can be used in all those applications where measuring distance to the target by establishing a physical contact is not possible. Typical examples include measuring presence of objects on a conveyor belt in logistic centers, ensuring safety distances around moving robot arms among many others.
TIDEP0069 66AK2G02 DSP + ARM Processor Audio Processing Reference Design | TI.com
TIDEP0069: The TIDEP0069 TI Reference Design is a reference platform based on the 66AK2G02 DSP + ARM processor System-On-Chip (SoC) and companion AIC3106 Audio codec and enables a quick path to audio processing algorithm design and demonstration. This audio solution design includes real time application software using the Processor SDK TI RTOS software that demonstrates audio processing block on the DSP to add audio effects.
TIDEP0036 Reference Design using TMS320C6657 to Implement Efficient OPUS Codec Solution | TI.com
TIDEP0036: The TIDEP0036 reference design provides an example of the ease of running TI optimized Opus encoder/decoder on the TMS320C6657 device. Since Opus supports a a wide range of bit rates, frame sizes and sampling rates, all with low delay, it has applicability for voice communications, networked audio and even high performance audio processing application. This design also highlights the performance improvements achieved when implementing the Opus codec on a DSP vs. a general purpose processor, like ARM. Depending upon the level of optimization of the code running on the genral purpose processor, implementing the Opus Codec on a C66x TI DSP core can have 3X the performance of an ARM CORTEX A-15 implementation. TMS320C66x DSPs support both audio and video codecs.
TIDEP0068 PCI Express PCB Design Considerations Reference Design for the 66AK2G02 General Purpose EVM 'GP EVM' | TI.com
TIDEP0068: PCI-Express provides for low pin-count, high reliability, and high-speed with data transfer at rates of up to 5.0 Gbps per lane, per direction, and an PCIe module is included on the TI 66AK2G02 DSP + ARM Processor system on chip (SoC). This PCIe PCB design considerations reference design helps developers optimize the printed circuit board (PCB) design by providing best-practice PCB for the PCIe portion of the 66AK2G02 Processor SoC. This in turn enables developers achieve desired PCIe signal performance on the first PCB implementation pass, allowing rapid focus on K2G Processor based application development and test. The 66AK2G02 General Purpose EVM (EVMK2G) is used as a reference to discuss some of these considerations.
Monte-Carlo Simulation on AM57x Using OpenCL for DSP Acceleration Reference Design
TIDEP0046: TI’s high performance ARM® Cortex®-A15 based AM57x processors also integrate C66x DSPs. These DSPs were designed to handle high signal and data processing tasks that are often required by industrial, automotive and financial applications. The AM57x OpenCL implementation makes it easy for users to utilize DSP acceleration for high computational tasks while using a standard programming model and language, thereby removing the need for deep knowledge of the DSP architecture. The TIDEP0046 TI reference design provides an example of using DSP acceleration to generate a very long sequence of normal random numbers using standard C/C++ code.
Sercos III Communications Development Platform
TIDEP0010: The TIDEP0010 Sercos III communication development platform combines the AM335x Sitara processor family from Texas Instruments (TI) and the Sercos III media access control (MAC) layer into a single system-on-chip (SoC) solution. Targeted for Sercos III slave communications, the TIDEP0010 allows designers to implement the real-time Sercos III communication standard for a broad range of industrial automation equipment. The design is based on the TMDSICE3359 Industrial Communications Engine (ICE).
SDI Video Aggregation Reference Design
TIDA-00352: This verified reference design is a complete four channel SDI aggregation and de-aggregation solution. One TLK10022 is used to aggregate four synchronous HD-SDI sources together into one 5.94 Gbps serial link. The serial data is transferred via copper or optical fiber where a second TLK10022 is used to de-aggregate and seamlessly redisplay the original video content.
TIDA-00309 DisplayPort Video 4:1 Aggregation Reference Design | TI.com
TIDA-00309: This verified reference design is a complete four channel DisplayPort aggregation and de-aggregation solution. One TLK10022 is used to aggregate four synchronous DisplayPort (DP) sources together into one 10.8 Gbps serial link. The serial data is transferred via copper or optical fiber where a second TLK10022 is used to de-aggregate and seamlessly redisplay the original video content.
TIDEP0078 OPC UA Data Access Server for AM572x Reference Design | TI.com
TIDEP0078: OPC UA is an industrial machine-to-machine protocol designed to allow interoperability and communication between all machines connected under Industry 4.0. The TIDEP0078 TI Design demonstrates use of the MatrikonOPC™ OPC UA server development kit (SDK) to allow communications using an OPC UA data access (DA) server running embedded in a project or design. The OPC UA DA deals with real-time data and is best suited for industrial automation applications where time is an important aspect of the data. A reference OPC UA server implementation is provided that accesses the GPIO capabilities of the AM572x IDK. The reference code can be extended to provide an OPC UA interface to any data the AM572x IDK board can access including data acquired through Profibus, RS-485, CAN bus, and industrial Ethernet-based protocols such as EtherCAT™ or PROFINET™ using the Programmable Real-time Unit Industrial Communication Subsystems (PRU-ICSS).
