参考设计
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Power and Thermal Design Considerations Using TI's AM57x Processor Reference Design
TIDEP0047: This TI Design (TIDEP0047) is a reference platform based on the AM57x processor and companion TPS659037 power management integrated circuit (PMIC). This TI Design specifically highlights important power and thermal design considerations and techniques for systems designed with AM57x and TPS659037. It includes reference material and documentation covering power management design, power distribution network (PDN) design considerations, thermal design considerations, estimating power consumption, and a power consumption summary.
Arria V Power Reference Design - PMP8610.1 - TI Tool Folder
PMP8610: Power Solution Reference Design for Arria V FPGA from Altera. This solution uses integrated inductor modules for ease of use to help design power solution for Arria V FPGA from Altera. This design incorporate sequencing need for the PFGA as well. Go to the TPS84 to LMZ3 part number cross reference.
PMP7975 Analog Solution for Zynq | TI.com
PMP7975: Xilinx chose TI as the power solution vendor to power Zynq FPGA (along with other analog solution from TI). You will find Schematic and bill of material fo the solution Xilinx used on the development kits.
Altera Arria V SoC Power Supply Reference Design
PMP9360.6: This reference design provides all the power supply rails necessary to power Altera's Arria V SoC FPGA. This design uses LMZ3 series modules to generate the rails to power the FPGA.
TIDA-00204 EMI/EMC Compliant Industrial Temp Dual Port Gigabit Ethernet PHY Reference Design | TI.com
TIDA-00204: This design allows for performance evaluation of two industrial grade DP83867IR Gigabit Ethernet PHYs and Sitara™ host processors with integrated Ethernet MAC and Switch. It was developed to meet industrial requirements for EMI and EMC. The application firmware implements a driver for the PHY, UDP and TCP/IP stack and HTTP web server examples. The host processor is configured to boot the pre-installed firmware from on-board SD-Card. A USB virtual COM port offers optional access to the PHYs registers. A JTAG interface allows for own firmware development.
PMP8610 Arria V Power Reference Design | TI.com
PMP8610: Power Solution Reference Design for Arria V FPGA from Altera. This solution uses integrated inductor modules for ease of use to help design power solution for Arria V FPGA from Altera. This design incorporate sequencing need for the PFGA as well. Go to the TPS84 to LMZ3 part number cross reference.
Xilinx Artix 7 FPGA with PMBus Power Management Reference Design
PMP7977: The Artix 7 power management reference design board uses power modules, linear regulators, and a PMBus compliant system controller to supply all required core and auxiliary voltages needed by the FPGA, including DDR memory termination. A Digital Power graphical user interface is used to monitor the voltage and current levels of the board’s power rails.
Power Reference Design for Xilinx® Zynq®-7000 - PMP7877.5 - TI Tool Folder
PMP7877: The PMP7877 reference design provides all the rails necessary to power a Xilinx® Zynq®-7000 series SoC. It operates from an input voltage range of 10.8Vin to 13.2Vin and has seven regulated outputs: 1Vout @ 5A, 1.8Vout @ 2.5A, 1.5Vout @ 6A, 3.3Vout @ 5A, 3.3Vout @ 5A, 5Vout @ 2A, and 0.75Vout @ 1A continous/3Apeak. This design has been approved and tested by Xilinx.
TIDEP0047 Power and Thermal Design Considerations Using TI's AM57x Processor Reference Design | TI.com
TIDEP0047: This TI Design (TIDEP0047) is a reference platform based on the AM57x processor and companion TPS659037 power management integrated circuit (PMIC). This TI Design specifically highlights important power and thermal design considerations and techniques for systems designed with AM57x and TPS659037. It includes reference material and documentation covering power management design, power distribution network (PDN) design considerations, thermal design considerations, estimating power consumption, and a power consumption summary.
Altera Arria V GZ FPGA Discrete Power Solution Reference Design
PMP9357: The PMP9357 reference design is a complete power solution for Altera's Arria V series FPGAs. This design uses several TPS54620 synchronous step down converters, LDOs, and a DDR termination regulator to provide all the necessary rails to power the FPGA. To provide correct power sequencing, a UCD90120A power supply sequencer/monitor is used and can be controlled through I2C.
Altera Arria V GX FPGA Power Solution Reference Design
PMP9449: The PMP9449 reference design provides all the power supply rails necessary to power Altera's Arria® V GX family of FPGAs. It utilizes a TPS38600 to monitor the input supply and provide power on sequencing. This design features low cost, small footprint discrete ICs and is powered from a single 5V input.
Smart Home and Energy Gateway Reference Design
TIEP-SMART-ENERGY-GATEWAY: The Smart Home and Energy Gateway Reference Design provides example implementation for measurement, management and communication of energy systems for smart homes and buildings. This example design is a bridge between different communication interfaces, such as WiFi, Ethernet, ZigBee or Bluetooth, that are commonly found in residential and commercial buildings. Since objects in the house and buildings are becoming more and more connected, the gateway design needs to be flexible to accommodate different RF standard, since no single RF standard is dominating the market. This example gateway addresses this problem by supporting existing legacy RF standards (WiFi, Bluetooth) and newer RF standards (ZigBee, BLE).
Power Reference Design for Xilinx® Zynq®-7000
PMP7877.2: The PMP7877 reference design provides all the rails necessary to power a Xilinx® Zynq®-7000 series SoC. It operates from an input voltage range of 10.8Vin to 13.2Vin and has seven regulated outputs: 1Vout @ 5A, 1.8Vout @ 2.5A, 1.5Vout @ 6A, 3.3Vout @ 5A, 3.3Vout @ 5A, 5Vout @ 2A, and 0.75Vout @ 1A continous/3Apeak. This design has been approved and tested by Xilinx.
PMP9449 Altera Arria V GX FPGA Power Solution Reference Design | TI.com
PMP9449: The PMP9449 reference design provides all the power supply rails necessary to power Altera's Arria® V GX family of FPGAs. It utilizes a TPS38600 to monitor the input supply and provide power on sequencing. This design features low cost, small footprint discrete ICs and is powered from a single 5V input.
Reference Design using TMS320C6657 to Implement Efficient OPUS Codec Solution
TIDEP0036: The TIDEP0036 reference design provides an example of the ease of running TI optimized Opus encoder/decoder on the TMS320C6657 device. Since Opus supports a a wide range of bit rates, frame sizes and sampling rates, all with low delay, it has applicability for voice communications, networked audio and even high performance audio processing application. This design also highlights the performance improvements achieved when implementing the Opus codec on a DSP vs. a general purpose processor, like ARM. Depending upon the level of optimization of the code running on the genral purpose processor, implementing the Opus Codec on a C66x TI DSP core can have 3X the performance of an ARM CORTEX A-15 implementation. TMS320C66x DSPs support both audio and video codecs.
TIDEP0054 Parallel Redundancy Protocol (PRP) Ethernet Reference Design for Substation Automation | TI.com
TIDEP0054: This TI Design implements a solution for high-reliability, low-latency network communications for substation automation equipment in Smart Grid transmission and distribution networks. It supports the Parallel Redundancy Protocol (PRP) specification in the IEC 62439 standard using the PRU-ICSS. This solution is a lower-cost alternative to FPGA approaches and provides the flexibility and performance to add features such as IEC 61850 support without additional components.
Arria V Power Reference Design
PMP8610.2: Power Solution Reference Design for Arria V FPGA from Altera. This solution uses integrated inductor modules for ease of use to help design power solution for Arria V FPGA from Altera. This design incorporate sequencing need for the PFGA as well. Go to the TPS84 to LMZ3 part number cross reference.
TIDEP0050 EnDat 2.2 System Reference Design | TI.com
TIDEP0050: The TIDEP0050 TI Design implements the EnDat 2.2 Master protocol stack and hardware interface solution based on the HEIDENHAIN EnDat 2.2 standard for position or rotary encoders. The design is composed of the EnDat 2.2 Master protocol stack, half-duplex communications using RS485 transceivers and the line termination implemented on the Sitara AM437x Industrial Development Kit. This design is fully tested to meet the HEIDENHAIN EnDat 2.2 standard. Along with EnDat position feedback, the AM437x IDK is also able to support industrial communications and motor drive as described in the AM437x Single-Chip Motor-Control Design Guide.
Arria V Power Reference Design
PMP8610.1: Power Solution Reference Design for Arria V FPGA from Altera. This solution uses integrated inductor modules for ease of use to help design power solution for Arria V FPGA from Altera. This design incorporate sequencing need for the PFGA as well. Go to the TPS84 to LMZ3 part number cross reference.
PMP7978 Analog Solution for Kintex 7 | TI.com
PMP7978: Xilinx chose TI as the power solution vendor to power Kintex 7 FPGA (along with other analog solution from TI). You will find Schematic and bill of material fo the solution Xilinx used on the development kits.
SPARTAN-6-LX150T-REF Spartan-6 LX150T Dev Kit | TI.com
SPARTAN-6-LX150T-REF: Made in partnership with Avnet and Xilinx, the Spartan-6 LX150T Development Kit provides a complete development platform for the Spartan-6 LXT FPGA family. The Spartan-6 LX150T includes onboard serial gigabit transceiver interface interfaces (GTP) which, when used with the appropriate FPGA IP, enable support for PCI Express or SATA. The board also includes FMC expansion slots to extend the application specific functions.
Spartan-6 LX150T Dev Kit
SPARTAN-6-LX150T-REF: Made in partnership with Avnet and Xilinx, the Spartan-6 LX150T Development Kit provides a complete development platform for the Spartan-6 LXT FPGA family. The Spartan-6 LX150T includes onboard serial gigabit transceiver interface interfaces (GTP) which, when used with the appropriate FPGA IP, enable support for PCI Express or SATA. The board also includes FMC expansion slots to extend the application specific functions.
Arria V Power Reference Design
PMP8610.4: Power Solution Reference Design for Arria V FPGA from Altera. This solution uses integrated inductor modules for ease of use to help design power solution for Arria V FPGA from Altera. This design incorporate sequencing need for the PFGA as well. Go to the TPS84 to LMZ3 part number cross reference.
PMP7976 Analog Solution for Virtex 7 | TI.com
PMP7976: Xilinx chose TI as the power solution vendor to power Virtex 7 FPGA (along with other analog solution from TI). You will find Schematic and bill of material fo the solution Xilinx used on the development kits.
Arria V Power Reference Design
PMP8610.3: Power Solution Reference Design for Arria V FPGA from Altera. This solution uses integrated inductor modules for ease of use to help design power solution for Arria V FPGA from Altera. This design incorporate sequencing need for the PFGA as well. Go to the TPS84 to LMZ3 part number cross reference.
Power Reference Design for Xilinx® Zynq®-7000
PMP7877.5: The PMP7877 reference design provides all the rails necessary to power a Xilinx® Zynq®-7000 series SoC. It operates from an input voltage range of 10.8Vin to 13.2Vin and has seven regulated outputs: 1Vout @ 5A, 1.8Vout @ 2.5A, 1.5Vout @ 6A, 3.3Vout @ 5A, 3.3Vout @ 5A, 5Vout @ 2A, and 0.75Vout @ 1A continous/3Apeak. This design has been approved and tested by Xilinx.
Arria V Power Reference Design - PMP8610.7 - TI Tool Folder
PMP8610: Power Solution Reference Design for Arria V FPGA from Altera. This solution uses integrated inductor modules for ease of use to help design power solution for Arria V FPGA from Altera. This design incorporate sequencing need for the PFGA as well. Go to the TPS84 to LMZ3 part number cross reference.
TIDEP0025 Single Chip Drive for Industrial Communications and Motor Control | TI.com
TIDEP0025: This TI design implements a hardware interface solution based on the HEIDENHAIN EnDat 2.2 standard for position or rotary encoders. The platform also allows designers to implement real-time EtherCAT communications standards in a broad range of industrial automation equipment. It enables designers with a low foot print, low power and single chip solution in applications such as industrial automation, factory automation or industrial communication.
Power for Altera Cyclone V (Cyclone 5) FPGA
PMP8571: PMP8571 is an easy to use power solution designed using integrated inductor power modules for Altera’s Cyclone 5 FPGA. This design used TPS84621 and TPS84320 along with TPS51200 to generate 5 rails to power the FPGA.
Arria V Power Reference Design - PMP8610.2 - TI Tool Folder
PMP8610: Power Solution Reference Design for Arria V FPGA from Altera. This solution uses integrated inductor modules for ease of use to help design power solution for Arria V FPGA from Altera. This design incorporate sequencing need for the PFGA as well. Go to the TPS84 to LMZ3 part number cross reference.
TIDEP0076 3D Machine Vision Reference Design Based on AM572x Processor with DLP® Structured Light | TI.com
TIDEP0076: The TIDEP0076 3D machine vision design describes an embedded 3D scanner based on the structured light principle. A digital camera along with a Sitara™ AM57xx processor System on Chip (SoC) is used to capture reflected light patterns from a DLP4500-based projector. Subsquent processing of captured patterns, calculation of the object's 3D point cloud and its 3D visualization are all performed within the AM57xx processor SoC. This design provides an embedded solution with advantages in power, simplicity, cost and size over a host PC-based implementation.
Analog Solution for Kintex 7
PMP7978: Xilinx chose TI as the power solution vendor to power Kintex 7 FPGA (along with other analog solution from TI). You will find Schematic and bill of material fo the solution Xilinx used on the development kits.
PMP9353 Altera Cyclone V SoC Power Supply Reference Design | TI.com
PMP9353: The PMP9353 reference design is a complete power solution for Altera Cyclone V SoC devices. This design uses several LMZ3 series modules , two LDOs, and a DDR termination regulator to provide all the necessary rails to power the SoC chip. This design also shows correct power-up sequencing.
Arria V Power Reference Design
PMP8610: Power Solution Reference Design for Arria V FPGA from Altera. This solution uses integrated inductor modules for ease of use to help design power solution for Arria V FPGA from Altera. This design incorporate sequencing need for the PFGA as well. Go to the TPS84 to LMZ3 part number cross reference.
Power Reference Design for Xilinx® Zynq®-7000 - PMP7877.7 - TI Tool Folder
PMP7877: The PMP7877 reference design provides all the rails necessary to power a Xilinx® Zynq®-7000 series SoC. It operates from an input voltage range of 10.8Vin to 13.2Vin and has seven regulated outputs: 1Vout @ 5A, 1.8Vout @ 2.5A, 1.5Vout @ 6A, 3.3Vout @ 5A, 3.3Vout @ 5A, 5Vout @ 2A, and 0.75Vout @ 1A continous/3Apeak. This design has been approved and tested by Xilinx.
PMP7977 Xilinx Artix 7 FPGA with PMBus Power Management Reference Design | TI.com
PMP7977: The Artix 7 power management reference design board uses power modules, linear regulators, and a PMBus compliant system controller to supply all required core and auxiliary voltages needed by the FPGA, including DDR memory termination. A Digital Power graphical user interface is used to monitor the voltage and current levels of the board’s power rails.
Reference Design for Telecom Applications (24V @ 0.5A)
PMP4742.2: PMP4742.2 is a simple and efficient non synchronous boost converter. It boosts the input 12V to 24V at 150mA nominal, 500mA maximum. Its enable pin is driven by power good signal from the hot swap TPS2420.
Single Chip Drive for Industrial Communications and Motor Control
TIDEP0025: This TI design implements a hardware interface solution based on the HEIDENHAIN EnDat 2.2 standard for position or rotary encoders. The platform also allows designers to implement real-time EtherCAT communications standards in a broad range of industrial automation equipment. It enables designers with a low foot print, low power and single chip solution in applications such as industrial automation, factory automation or industrial communication.
TIDEP0046 Monte-Carlo Simulation on AM57x Using OpenCL for DSP Acceleration Reference Design | TI.com
TIDEP0046: TI’s high performance ARM® Cortex®-A15 based AM57x processors also integrate C66x DSPs. These DSPs were designed to handle high signal and data processing tasks that are often required by industrial, automotive and financial applications. The AM57x OpenCL implementation makes it easy for users to utilize DSP acceleration for high computational tasks while using a standard programming model and language, thereby removing the need for deep knowledge of the DSP architecture. The TIDEP0046 TI reference design provides an example of using DSP acceleration to generate a very long sequence of normal random numbers using standard C/C++ code.
PMP9365 Altera® Stratix® V FPGA Power Solution | TI.com
PMP9365: The PMP9365 reference design provides all the power supply rails necessary to power Altera's Stratix V family of FPGAs. This design uses several LMZ3 series modules, LDOs, and a DDR termination regulator to provide all the necessary rails to power the FPGA. It also features two LM3880's for flexible power up and power down sequencing. This design uses a 12V input.
Altera® Stratix® V FPGA Power Solution
PMP9365: The PMP9365 reference design provides all the power supply rails necessary to power Altera's Stratix V family of FPGAs. This design uses several LMZ3 series modules, LDOs, and a DDR termination regulator to provide all the necessary rails to power the FPGA. It also features two LM3880's for flexible power up and power down sequencing. This design uses a 12V input.
EnDat 2.2 System Reference Design
TIDEP0050: The TIDEP0050 TI Design implements the EnDat 2.2 Master protocol stack and hardware interface solution based on the HEIDENHAIN EnDat 2.2 standard for position or rotary encoders. The design is composed of the EnDat 2.2 Master protocol stack, half-duplex communications using RS485 transceivers and the line termination implemented on the Sitara AM437x Industrial Development Kit. This design is fully tested to meet the HEIDENHAIN EnDat 2.2 standard. Along with EnDat position feedback, the AM437x IDK is also able to support industrial communications and motor drive as described in the AM437x Single-Chip Motor-Control Design Guide.
Analog Solution for Virtex 7
PMP7976: Xilinx chose TI as the power solution vendor to power Virtex 7 FPGA (along with other analog solution from TI). You will find Schematic and bill of material fo the solution Xilinx used on the development kits.
Arria V Power Reference Design
PMP8610.7: Power Solution Reference Design for Arria V FPGA from Altera. This solution uses integrated inductor modules for ease of use to help design power solution for Arria V FPGA from Altera. This design incorporate sequencing need for the PFGA as well. Go to the TPS84 to LMZ3 part number cross reference.
Power Reference Design for Xilinx® Zynq®-7000
PMP7877: The PMP7877 reference design provides all the rails necessary to power a Xilinx® Zynq®-7000 series SoC. It operates from an input voltage range of 10.8Vin to 13.2Vin and has seven regulated outputs: 1Vout @ 5A, 1.8Vout @ 2.5A, 1.5Vout @ 6A, 3.3Vout @ 5A, 3.3Vout @ 5A, 5Vout @ 2A, and 0.75Vout @ 1A continous/3Apeak. This design has been approved and tested by Xilinx.
Power Reference Design for Xilinx® Zynq®-7000
PMP7877.4: The PMP7877 reference design provides all the rails necessary to power a Xilinx® Zynq®-7000 series SoC. It operates from an input voltage range of 10.8Vin to 13.2Vin and has seven regulated outputs: 1Vout @ 5A, 1.8Vout @ 2.5A, 1.5Vout @ 6A, 3.3Vout @ 5A, 3.3Vout @ 5A, 5Vout @ 2A, and 0.75Vout @ 1A continous/3Apeak. This design has been approved and tested by Xilinx.
PMP9357 Altera Arria V FPGA Power Supply Reference Design | TI.com
PMP9357: The PMP9357 reference design is a complete power solution for Altera's Arria V series FPGAs. This design uses several TPS54620 synchronous step down converters, LDOs, and a DDR termination regulator to provide all the necessary rails to power the FPGA. To provide correct power sequencing, a UCD90120A power supply sequencer/monitor is used and can be controlled through I2C.
Power Reference Design for Xilinx® Zynq®-7000
PMP7877.3: The PMP7877 reference design provides all the rails necessary to power a Xilinx® Zynq®-7000 series SoC. It operates from an input voltage range of 10.8Vin to 13.2Vin and has seven regulated outputs: 1Vout @ 5A, 1.8Vout @ 2.5A, 1.5Vout @ 6A, 3.3Vout @ 5A, 3.3Vout @ 5A, 5Vout @ 2A, and 0.75Vout @ 1A continous/3Apeak. This design has been approved and tested by Xilinx.
EMI/EMC Compliant Industrial Temp Dual Port Gigabit Ethernet Reference Design
TIDA-00204: This design allows for performance evaluation of two industrial grade DP83867IR Gigabit Ethernet PHYs and Sitara™ host processors with integrated Ethernet MAC and Switch. It was developed to meet industrial requirements for EMI and EMC. The application firmware implements a driver for the PHY, UDP and TCP/IP stack and HTTP web server examples. The host processor is configured to boot the pre-installed firmware from on-board SD-Card. A USB virtual COM port offers optional access to the PHYs registers. A JTAG interface allows for own firmware development.
TIDEP0036 Reference Design using TMS320C6657 to Implement Efficient OPUS Codec Solution | TI.com
TIDEP0036: The TIDEP0036 reference design provides an example of the ease of running TI optimized Opus encoder/decoder on the TMS320C6657 device. Since Opus supports a a wide range of bit rates, frame sizes and sampling rates, all with low delay, it has applicability for voice communications, networked audio and even high performance audio processing application. This design also highlights the performance improvements achieved when implementing the Opus codec on a DSP vs. a general purpose processor, like ARM. Depending upon the level of optimization of the code running on the genral purpose processor, implementing the Opus Codec on a C66x TI DSP core can have 3X the performance of an ARM CORTEX A-15 implementation. TMS320C66x DSPs support both audio and video codecs.
PMP8610 Arria V Power Reference Design | TI.com
PMP8610: Power Solution Reference Design for Arria V FPGA from Altera. This solution uses integrated inductor modules for ease of use to help design power solution for Arria V FPGA from Altera. This design incorporate sequencing need for the PFGA as well. Go to the TPS84 to LMZ3 part number cross reference.
PMP9357 Altera Arria V FPGA Power Supply Reference Design | TI.com
PMP9357: The PMP9357 reference design is a complete power solution for Altera's Arria V series FPGAs. This design uses several TPS54620 synchronous step down converters, LDOs, and a DDR termination regulator to provide all the necessary rails to power the FPGA. To provide correct power sequencing, a UCD90120A power supply sequencer/monitor is used and can be controlled through I2C.
Arria V Power Reference Design
PMP8610.5: Power Solution Reference Design for Arria V FPGA from Altera. This solution uses integrated inductor modules for ease of use to help design power solution for Arria V FPGA from Altera. This design incorporate sequencing need for the PFGA as well. Go to the TPS84 to LMZ3 part number cross reference.
Altera Cyclone V SoC FPGA Power Reference Design
PMP9353: The PMP9353 reference design is a complete power solution for Altera Cyclone V SoC devices. This design uses several LMZ3 series modules , two LDOs, and a DDR termination regulator to provide all the necessary rails to power the SoC chip. This design also shows correct power-up sequencing.
TIEP-SMART-ENERGY-GATEWAY Smart Home and Energy Gateway Reference Design | TI.com
TIEP-SMART-ENERGY-GATEWAY: The Smart Home and Energy Gateway Reference Design provides example implementation for measurement, management and communication of energy systems for smart homes and buildings. This example design is a bridge between different communication interfaces, such as WiFi, Ethernet, ZigBee or Bluetooth, that are commonly found in residential and commercial buildings. Since objects in the house and buildings are becoming more and more connected, the gateway design needs to be flexible to accommodate different RF standard, since no single RF standard is dominating the market. This example gateway addresses this problem by supporting existing legacy RF standards (WiFi, Bluetooth) and newer RF standards (ZigBee, BLE).
Power Reference Design for Xilinx® Zynq®-7000
PMP7877.6: The PMP7877 reference design provides all the rails necessary to power a Xilinx® Zynq®-7000 series SoC. It operates from an input voltage range of 10.8Vin to 13.2Vin and has seven regulated outputs: 1Vout @ 5A, 1.8Vout @ 2.5A, 1.5Vout @ 6A, 3.3Vout @ 5A, 3.3Vout @ 5A, 5Vout @ 2A, and 0.75Vout @ 1A continous/3Apeak. This design has been approved and tested by Xilinx.
Monte-Carlo Simulation on AM57x Using OpenCL for DSP Acceleration Reference Design
TIDEP0046: TI’s high performance ARM® Cortex®-A15 based AM57x processors also integrate C66x DSPs. These DSPs were designed to handle high signal and data processing tasks that are often required by industrial, automotive and financial applications. The AM57x OpenCL implementation makes it easy for users to utilize DSP acceleration for high computational tasks while using a standard programming model and language, thereby removing the need for deep knowledge of the DSP architecture. The TIDEP0046 TI reference design provides an example of using DSP acceleration to generate a very long sequence of normal random numbers using standard C/C++ code.
PMP7877 Power Reference Design for Xilinx® Zynq®-7000 | TI.com
PMP7877: The PMP7877 reference design provides all the rails necessary to power a Xilinx® Zynq®-7000 series SoC. It operates from an input voltage range of 10.8Vin to 13.2Vin and has seven regulated outputs: 1Vout @ 5A, 1.8Vout @ 2.5A, 1.5Vout @ 6A, 3.3Vout @ 5A, 3.3Vout @ 5A, 5Vout @ 2A, and 0.75Vout @ 1A continous/3Apeak. This design has been approved and tested by Xilinx.
Altera Arria V SoC FPGA Power Solution Reference Design
PMP9360: The PMP9360 reference design is a complete power solution for Altera's Arria V™ SoC devices. This design uses several LMZ3 series modules , an LDO, and a DDR termination regulator to provide all the necessary rails to power the SoC chip. This design also shows correct power up sequencing.
Reference Design for Telecom Applications (12V @ 1.1A)
PMP4742.1: PMP4742.1 comprises a negative input (-10.8V to -13.2V) to positive output (12V@1A average) inverting buck-boost converter with TPS40210; a hot swap circuit with TPS2420 quickly limits the output current to 2A peak.
Analog Solution for Zynq
PMP7975: Xilinx chose TI as the power solution vendor to power Zynq FPGA (along with other analog solution from TI). You will find Schematic and bill of material fo the solution Xilinx used on the development kits.
Reference Design for Telecom Applications (3.3V @ 5A)
PMP4742.3: PMP4742.3 protects the 12Vin by means of hot swap controller (TPS2420) and feeds a TPS54620, syncronous buck converter, which generates 3.3V@3.7A. An INA210 reads the buck's current for monitoring purposes.
PMP7877 Power Reference Design for Xilinx® Zynq®-7000 | TI.com
PMP7877: The PMP7877 reference design provides all the rails necessary to power a Xilinx® Zynq®-7000 series SoC. It operates from an input voltage range of 10.8Vin to 13.2Vin and has seven regulated outputs: 1Vout @ 5A, 1.8Vout @ 2.5A, 1.5Vout @ 6A, 3.3Vout @ 5A, 3.3Vout @ 5A, 5Vout @ 2A, and 0.75Vout @ 1A continous/3Apeak. This design has been approved and tested by Xilinx.
Power Reference Design for Xilinx® Zynq®-7000
PMP7877.1: The PMP7877 reference design provides all the rails necessary to power a Xilinx® Zynq®-7000 series SoC. It operates from an input voltage range of 10.8Vin to 13.2Vin and has seven regulated outputs: 1Vout @ 5A, 1.8Vout @ 2.5A, 1.5Vout @ 6A, 3.3Vout @ 5A, 3.3Vout @ 5A, 5Vout @ 2A, and 0.75Vout @ 1A continous/3Apeak. This design has been approved and tested by Xilinx.
Arria V Power Reference Design
PMP8610.6: Power Solution Reference Design for Arria V FPGA from Altera. This solution uses integrated inductor modules for ease of use to help design power solution for Arria V FPGA from Altera. This design incorporate sequencing need for the PFGA as well. Go to the TPS84 to LMZ3 part number cross reference.
PMP9353 Altera Cyclone V SoC Power Supply Reference Design | TI.com
PMP9353: The PMP9353 reference design is a complete power solution for Altera Cyclone V SoC devices. This design uses several LMZ3 series modules , two LDOs, and a DDR termination regulator to provide all the necessary rails to power the SoC chip. This design also shows correct power-up sequencing.
TIDEP0078 OPC UA Data Access Server for AM572x Reference Design | TI.com
TIDEP0078: OPC UA is an industrial machine-to-machine protocol designed to allow interoperability and communication between all machines connected under Industry 4.0. The TIDEP0078 TI Design demonstrates use of the MatrikonOPC™ OPC UA server development kit (SDK) to allow communications using an OPC UA data access (DA) server running embedded in a project or design. The OPC UA DA deals with real-time data and is best suited for industrial automation applications where time is an important aspect of the data. A reference OPC UA server implementation is provided that accesses the GPIO capabilities of the AM572x IDK. The reference code can be extended to provide an OPC UA interface to any data the AM572x IDK board can access including data acquired through Profibus, RS-485, CAN bus, and industrial Ethernet-based protocols such as EtherCAT™ or PROFINET™ using the Programmable Real-time Unit Industrial Communication Subsystems (PRU-ICSS).
Power Reference Design for Xilinx® Zynq®-7000
PMP7877.7: The PMP7877 reference design provides all the rails necessary to power a Xilinx® Zynq®-7000 series SoC. It operates from an input voltage range of 10.8Vin to 13.2Vin and has seven regulated outputs: 1Vout @ 5A, 1.8Vout @ 2.5A, 1.5Vout @ 6A, 3.3Vout @ 5A, 3.3Vout @ 5A, 5Vout @ 2A, and 0.75Vout @ 1A continous/3Apeak. This design has been approved and tested by Xilinx.
Power for Altera Cyclone V (Cyclone 5) FPGA (2.5V@3.5A)
PMP8571.1: PMP8571.1 is an easy to use power solution designed using integrated inductor power modules for Altera’s Cyclone 5 FPGA. This design used TPS84621 and TPS84320 along with TPS51200 to generate 5 rails to power the FPGA.
