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首页 > 电子元器件选型 > 可编程逻辑 > 现场可编程门阵列

XC3S200AN-4FTG256C

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XC3S200AN-4FTG256C
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Field Programmable Gate Array, 448 CLBs, 200000 Gates, 280MHz, 4032-Cell, CMOS, PBGA256, 17 X 17 MM, ROHS COMPLIANT, FTBGA-256

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¥202.7179
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生命周期状态: Transferred
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XC3S1400 Xilinx 也适用于 XC3S1400AN ,XC3S1400AN-4FG676I ,XC3S1400AN-4FG676C 等其余29个型号 XC3S200AN-4FTG256C Xilinx 也适用于 XC3SD1800A-4CSG484C ,XC3S400AN-4FGG400C ,XC3S1400A-4FGG676C 等其余40个型号

参考设计

(1)
Reference Design using TMS320C6657 to Implement Efficient OPUS Codec Solution
TIDEP0036: The TIDEP0036 reference design provides an example of the ease of running TI optimized Opus encoder/decoder on the TMS320C6657 device. Since Opus supports a a wide range of bit rates, frame sizes and sampling rates, all with low delay, it has applicability for voice communications, networked audio and even high performance audio processing application. This design also highlights the performance improvements achieved when implementing the Opus codec on a DSP vs. a general purpose processor, like ARM. Depending upon the level of optimization of the code running on the genral purpose processor, implementing the Opus Codec on a C66x TI DSP core can have 3X the performance of an ARM CORTEX A-15 implementation. TMS320C66x DSPs support both audio and video codecs.
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