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参考设计(7)
Wideband RF-to-Digital Complex Receiver-Feedback Signal Chain
TIDA-00074: This is a wideband complex-receiver reference design and evaluation platform that is ideally suited for use as a feedback receiver for transmitter digital predistortion. The EVM signal chain is ideal for high intermediate-frequency (IF) complex-feedback applications and contains a complex demodulator, TI’s LMH6521 dual-channel DVGA and ADS5402 12-bit 800-MSPS dual-channel ADC. By modifying the onboard filter components, the signal chain is configurable for a variety of frequency plans. The EVM also includes TI’s LMK04808 dual-PLL clock jitter cleaner and generator to provide an onboard low-noise clocking solution. The LMH6521 DVGA gain is controlled through the GUI or alternatively through the high speed connector with an FPGA.
Basestation Transceiver with DPD Feedback Path
TIDA-00068: The design is for a small cell base station development platform. It provides two real receive paths, two complex transmit paths, and a shared real feedback path. This design has macro basestation performance, but with small cell base station footprint. The current design handles up to 20MHz of bandwidth.
Wideband Digital to RF Transmit Solution
TIDA-00072: The TSW308x is an example design of a wideband digital to RF transmit solution capable of generating 600 MHz of contiguous RF spectrum. The system provides a reference on how to use the DAC34x8x, TRF3705 IQ modulator and LMK0480x to achieve this. This reference EVM coupled with a pattern generator such as the TSW1400EVM can be used to arbitrarily generate narrow band and wideband signals at RF. Examples of configurations to generate standards compliant WCDMA test signals are provided.
Dual-Wideband RF-to-Digital Receiver Design
TIDA-00073: The TSW1265EVM is an example design of a wideband RF to digital dual receiver solution capable of digitizing up to 125MHz of spectrum. The system provides a reference on how to use the ADS4249, LMH6521, LMK0480x, and a dual mixer to achieve this. This reference EVEM coupled with a capture card such as the TSW1400 can be used to capture and analyze narrow band and wideband signals. Instructions are provided on how to change the LO and IF frequencies for different application needs. The TIDA-00073 was implemented with hardware from the TSW1265EVM.
16-bit 400KSPS 4-Ch. Multiplexed Data Acquisition Ref Design for High Voltage Inputs, Low Distortion
TIPD151: This TI Verified Design implements a 16-bit, differential 4-channel multiplexed data acquisition system at 400KSPS throughput for high voltage differential input of ±20 V (40 Vpk-pk) industrial applications. The circuit is realized with a 16-bit successive-approximation-resistor (SAR) analog-to-digital converter (ADC), a precision high voltage signal conditioning front end, and a 4-channel differential multiplexer (MUX). The design details the process for optimizing the precision high voltage front end drive circuit using the OPA192 and OPA140 to achieve excellent dynamic performance with the ADS8864.
Analog Interfacing Networks for DAC348x and Modulators
TIDA-00077: The analog interface circuits in this reference design are often used between current-source based digital-to analog converters (DAC) and quadrature modulators. While the DAC348x is used as an example of a TI high-speed DAC, the circuits can be applied to other current-source based converters with slight modifications. The DAC348x and TRF3705 analog interface are populated by default on the TSW308xEVMs. Both the DAC348x and TRF3705 are designed with the same DC bias and AC swing specification to provide a seamless interface. Other circuit topologies are described to account for other DC bias and AC swing specifications. By accounting the correct DC bias and proper AC swing, system designers can apply these circuits based on their application needs in order to achieve optimal performance.
Direct Down-Conversion System with I/Q Correction
TIDA-00078: The I/Q Correction block implemented in the Field Programmable Gate Array (FPGA) of the TSW6011EVM helps users to adopt a direct down conversion receiver architecture in a wireless system. The I/Q correction block consists of a single-tap blind algorithm, which corrects the frequency-independent I/Q imbalance in a complex zero-IF receiver system. Along with the I/Q correction block, the FPGA includes a digital gain block, a digital power-measurement block, x2 of interpolation block, an I/Q offset correction block, and a quadrature mixing block.
