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Thick Film Resistors – SMD; PANASONIC; ERJ-2RKF1002X; 10 kOhm; 0402; 1 %; Thick Film
制造商:
PANASONIC
制造商型号:
未知
符合标准:
未知
参考设计(17)
K2E Clock Generation Reference Design
TIDEP0026: A single clock source should not be used to drive multiple clock inputs for a high-performance processor device, such as multicore ARM Cortex-A15 based 66AK2Ex and AM5K2Ex processors, since excessive loading, reflections, and noise will negatively impact performance. These can be avoided through the use of a differential clock tree instead of a single clock source. This design demonstrates clock generation for the 66AK2Ex and AM5K2Ex families of KeyStone II ARM A15 + DSP and ARM-only multicore processors by use of a differential clock tree. This design shows a complete clock tree resulting in generation of all clocks needed for SoC cores and interfaces.
Altera Arria V GX FPGA Power Solution Reference Design
PMP9449: The PMP9449 reference design provides all the power supply rails necessary to power Altera's Arria® V GX family of FPGAs. It utilizes a TPS38600 to monitor the input supply and provide power on sequencing. This design features low cost, small footprint discrete ICs and is powered from a single 5V input.
Generating AVS SmartReflex Core Voltage for K2E Using TPS544C25 and PMBus Reference Design
TIDEP0042: The K2E requires the use of AVS SmartReflex control for the CVDD core voltage. This design provides method of generating the proper voltage using software and the PMBus interface of the TPS544C25. The circuit can be implemented on the XEVMK2EX.
Reference Design using TMS320C6657 to Implement Efficient OPUS Codec Solution
TIDEP0036: The TIDEP0036 reference design provides an example of the ease of running TI optimized Opus encoder/decoder on the TMS320C6657 device. Since Opus supports a a wide range of bit rates, frame sizes and sampling rates, all with low delay, it has applicability for voice communications, networked audio and even high performance audio processing application. This design also highlights the performance improvements achieved when implementing the Opus codec on a DSP vs. a general purpose processor, like ARM. Depending upon the level of optimization of the code running on the genral purpose processor, implementing the Opus Codec on a C66x TI DSP core can have 3X the performance of an ARM CORTEX A-15 implementation. TMS320C66x DSPs support both audio and video codecs.
Basestation Transceiver with DPD Feedback Path
TIDA-00068: The design is for a small cell base station development platform. It provides two real receive paths, two complex transmit paths, and a shared real feedback path. This design has macro basestation performance, but with small cell base station footprint. The current design handles up to 20MHz of bandwidth.
DAC Sample and Hold Glitch Reduction Reference Design
TIPD142: DAC R-2R architectures display great performance in regards to noise and accuracy, but at a cost of large glitch area. This design focuses on the reduction of major-carry glitches that occur from code specific transitions in DAC R-2R architectures. This design reduces this glitch area, making it suitable for glitch-sensitive applications such as waveform generation.
Wideband Digital to RF Transmit Solution
TIDA-00072: The TSW308x is an example design of a wideband digital to RF transmit solution capable of generating 600 MHz of contiguous RF spectrum. The system provides a reference on how to use the DAC34x8x, TRF3705 IQ modulator and LMK0480x to achieve this. This reference EVM coupled with a pattern generator such as the TSW1400EVM can be used to arbitrarily generate narrow band and wideband signals at RF. Examples of configurations to generate standards compliant WCDMA test signals are provided.
Optimizing LMH6554 to Drive High Speed ADCs
TIDA-00092: This reference design shows the ability of the high-speed amplifier, LMH6554, to perform single-ended to differential conversion to drive high-speed analog-to-digital converters (ADCs) while maintaining excellent noise and distortion performance. Performance versus input frequency is shown for both AC and DC coupled applications while interfaced to the ADS4449 quad, 250-MSPS, 14-bit ADC. Various options for common-mode voltages, power supplies, and interfaces are discussed and measured to meet the requirements of a variety of applications. Anti-aliasing filter examples are shown along with the performance improvements that they provide.
Dual-Wideband RF-to-Digital Receiver Design
TIDA-00073: The TSW1265EVM is an example design of a wideband RF to digital dual receiver solution capable of digitizing up to 125MHz of spectrum. The system provides a reference on how to use the ADS4249, LMH6521, LMK0480x, and a dual mixer to achieve this. This reference EVEM coupled with a capture card such as the TSW1400 can be used to capture and analyze narrow band and wideband signals. Instructions are provided on how to change the LO and IF frequencies for different application needs. The TIDA-00073 was implemented with hardware from the TSW1265EVM.
1-GHz Bandwidth Dual Channel Transmitter up to 4-GHz Reference Design
TIDA-00409: The TSW38J84 EVM reference design provides a platform to demonstrate a wideband dual transmit solution that incorporates an integrated LO. The reference design utilizes the 2.5 GSPS DAC38J84 device with the high performance modulators: TRF3722 (including integrated PLL/VCO) and TRF3705. The TRF3722 and TRF3705 can be combined to form a dual transmit solution with the TRF3722 generating the local oscillator (LO) for both modulators. The interface between the DAC38J84 and the modulators is discussed as well as measurements showing the combined performance of the DAC and modulators. The measurements illustrate the bandwidth performance, output third order intercept performance, harmonic distortion and sideband suppression performance.
Efficient, LDO-free Power Supply for a 12-bit 500-MSPS ADC Reference Design - PMP9767.2 - TI Tool Folder
PMP9767: The electrical performance of data converters depends on the cleanliness of their supply voltages. Linear regulators (LDOs) are commonly used but have low efficiency and high power loss, which is unsuitable for portable applications. Using a switch mode power supply (SMPS) instead, such as the TPS62231 and TPS62237, is a cost-effective and efficient power supply solution. Such a solution does not degrade the performance of the 12-bit ADS540x family of analog to digital converters (ADCs) and does not waste excessive power. The test report shows the Signal to Noise Ratio (SNR) and Spurious-Free Dynamic Range (SFDR) comparisons between the two power supplies, which demonstrate the same performance.
FPGA Firmware Project for Measuring Bit Errors in the Output Word of an A to D Converter
TIDA-00070: For applications where there are bit errors and resulting sample errors (also called sparkle codes, word errors, or code errors), the ability to measure the Error rates caused by these bit errors is important. This FPGA firmware based application note proposes a method to accurately measure these errors over an indefinite time and provides an example of how this measurement can be done using a simple FPGA platform. Code is available on request for the two examples described in the application note.
Wide-Bandwidth and High-Voltage Arbitrary Waveform Generator Front End
TIDA-00075: This design shows how to use an active interface with the current sink output of the DAC5682Z - typical applications for this include front ends for arbitrary waveform generators. The EVM includes the DAC5682Z for digital-to-analog conversion, an OPA695 to demonstrate an active interface implementation using a wide bandwidth operational amplifier and a THS3091 and THS3095 to showcase an operational amplifier with large voltage swing. Also included on board are a CDCM7005, VCXO and Reference for clock generation, and linear regulators for voltage regulation. Communication to the EVM is accomplished via a USB interface and GUI software.
12- to 24-V, 27-A Brushed DC Motor Reference Design
TIDA-00620: Brushed motors are a relatively popular option for motor designs because of their low price and simple control scheme. A brushed motor has a wire-wound rotor and permanent magnet stator. The commutation of the motor is achieved using conductive rings that are connected to the rotor using brushes that scrape against the commutator rings. This allows the direction of current through the motor to change based on the orientation of the brushes and different commutation rings. Utilizing an H-Bridge allows for easy direction and speed control changes to be applied quickly and efficiently to the brushed DC motor. An electronic drive is required to control the motor currents in a brushed DC motor. The electronic drive circuit consists of a power stage with two-phase inverter meeting the required power capability, a microcontroller to implement the motor speed commands and fault handling, current sensing for motor startup / stall protection, gate driver for controlling the two-phase inverter, and a power supply for microcontroller and other low voltage devices.
Synchronizing Multiple JESD204B ADCs for Emitter Position Location Reference Design
TIDA-00467: A common technique to estimate the position of emitters uses the amplitude and phase shift data of a signal derived from an array of spatially distributed sensors. For such systems, it is important to guarantee a deterministic phase relationship between the sensors to minimize errors in the actual measured data. This application design will discuss how multiple Analog to Digital Converters (ADCs) with a JESD204B interface can be synchronized so that the sampled data from the ADCs are phase aligned.
Generating AVS SmartReflex Core Voltage, PMBus for K2E Using TPS544C25 & LM10011 Reference Design
TIDEP0041: The K2E requires the use of AVS SmartReflex control for the CVDD core voltage. This design provides method of generating the proper voltage without the need for any software. The circuit is currently implemented on the XEVMK2EX.
Direct Down-Conversion System with I/Q Correction
TIDA-00078: The I/Q Correction block implemented in the Field Programmable Gate Array (FPGA) of the TSW6011EVM helps users to adopt a direct down conversion receiver architecture in a wireless system. The I/Q correction block consists of a single-tap blind algorithm, which corrects the frequency-independent I/Q imbalance in a complex zero-IF receiver system. Along with the I/Q correction block, the FPGA includes a digital gain block, a digital power-measurement block, x2 of interpolation block, an I/Q offset correction block, and a quadrature mixing block.
Maritex
分销商编号：
ERJ-2RKF1002X
交货地:
中国大陆
单价:
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-+
总计:
库存/包装：
123
起订量：
1
递增量：
1
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