参考设计(1)
Direct Down-Conversion System with I/Q Correction
TIDA-00078: The I/Q Correction block implemented in the Field Programmable Gate Array (FPGA) of the TSW6011EVM helps users to adopt a direct down conversion receiver architecture in a wireless system. The I/Q correction block consists of a single-tap blind algorithm, which corrects the frequency-independent I/Q imbalance in a complex zero-IF receiver system. Along with the I/Q correction block, the FPGA includes a digital gain block, a digital power-measurement block, x2 of interpolation block, an I/Q offset correction block, and a quadrature mixing block.
Avnet Americas
分销商编号：
ERJ-3EKF9761V
交货地:
中国大陆
港台地区
单价:
- 阶梯 人民币价格(含税) 美元价格
- 5000+ ¥0.0337 $0.0044
- 10000+ ¥0.0331 $0.0043
- 20000+ ¥0.0324 $0.0042
- 40000+ ¥0.0318 $0.0041
- 80000+ ¥0.0312 $0.0040
请输入数量：
-+
总计:
库存/包装：
80,000
/ Tape & Reel
起订量：
5,000
递增量：
5,000
备货时间：
15 Weeks, 0 Days
