参考设计
(6)
PMP7256 Power Management for C667x DSP AVS Core (CVDD) | TI.com
PMP7256: This reference design aims to supply the AVS core supply(CVDD) in the Keystone Multicore DSPs, mainly the C66x series. The C66x series uses SmartReflex technology to enable the DSP to control its supply voltage. In order to meet this requirement, this design combines a Synchronous Buck Converter (TPS56121) with the voltage Programmer for POL (LM10010). The LM10010 accepts a 6-bit VCNTL from the DSP and changes the output voltage of the TPS56121 to what the DSP requires.
Reference Design using TMS320C6657 to Implement Efficient OPUS Codec Solution
TIDEP0036: The TIDEP0036 reference design provides an example of the ease of running TI optimized Opus encoder/decoder on the TMS320C6657 device. Since Opus supports a a wide range of bit rates, frame sizes and sampling rates, all with low delay, it has applicability for voice communications, networked audio and even high performance audio processing application. This design also highlights the performance improvements achieved when implementing the Opus codec on a DSP vs. a general purpose processor, like ARM. Depending upon the level of optimization of the code running on the genral purpose processor, implementing the Opus Codec on a C66x TI DSP core can have 3X the performance of an ARM CORTEX A-15 implementation. TMS320C66x DSPs support both audio and video codecs.
PMP7303 Power Management for C667x DSP AVS Core (CVDD) | TI.com
PMP7303: The C667x power management reference design is optimized to power the core voltage (CVCC) of TI's Keystone multicore DSP. The C66x series uses SmartReflex technology to enable the DSP to control its supply voltage to attain optimal performance and low power consumption. The design features a 2-phase synchronous buck controller and NEXFET Power Block MOSFETs to acheive the highest efficiency and smallest form factor from a 5V or a 12V input supply.
Power Management for C667x DSP AVS Core (CVDD)
PMP7256: This reference design aims to supply the AVS core supply(CVDD) in the Keystone Multicore DSPs, mainly the C66x series. The C66x series uses SmartReflex technology to enable the DSP to control its supply voltage. In order to meet this requirement, this design combines a Synchronous Buck Converter (TPS56121) with the voltage Programmer for POL (LM10010). The LM10010 accepts a 6-bit VCNTL from the DSP and changes the output voltage of the TPS56121 to what the DSP requires.
Power Management for C667x DSP AVS Core (CVDD)
PMP7303: The C667x power management reference design is optimized to power the core voltage (CVCC) of TI's Keystone multicore DSP. The C66x series uses SmartReflex technology to enable the DSP to control its supply voltage to attain optimal performance and low power consumption. The design features a 2-phase synchronous buck controller and NEXFET Power Block MOSFETs to acheive the highest efficiency and smallest form factor from a 5V or a 12V input supply.
TIDEP0036 Reference Design using TMS320C6657 to Implement Efficient OPUS Codec Solution | TI.com
TIDEP0036: The TIDEP0036 reference design provides an example of the ease of running TI optimized Opus encoder/decoder on the TMS320C6657 device. Since Opus supports a a wide range of bit rates, frame sizes and sampling rates, all with low delay, it has applicability for voice communications, networked audio and even high performance audio processing application. This design also highlights the performance improvements achieved when implementing the Opus codec on a DSP vs. a general purpose processor, like ARM. Depending upon the level of optimization of the code running on the genral purpose processor, implementing the Opus Codec on a C66x TI DSP core can have 3X the performance of an ARM CORTEX A-15 implementation. TMS320C66x DSPs support both audio and video codecs.
