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首页 > 电子元器件选型 > 变压器 > 射频变压器

B0430J50100AHF

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B0430J50100AHF
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RF Transformer, 400MHz Min, 3000MHz Max, CHIP

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¥11.8447
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生命周期状态: Active
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Synchronization of JESD204B Giga-Sample ADCs using Xilinx Platform for Phased Array Radar Systems
TIDA-00432: This system level design shows how two ADC12J4000 evaluation modules (EVMs) can be synchronized together using a Xilinx VC707 platform. The design document describes the required hardware modifications and device configurations, including the clocking scheme. Example configuration files are shown for each EVM. The FPGA firmware is described and the relevant Xilinx IP block configuration parameters are shown. Data taken on the actual hardware is shown and analyzed, showing synchronization within 50 ps without characterized cables or calibrated propagation delays.
Schematic and Layout Recommendations for the Giga Sample Per Second (GSPS) ADC
TIDA-00071: This reference design is a guide to the schematics and layout for the system designer using a GSPS ADC in their system. Use this reference design along with the datasheet — the datasheet is always the final authority. Also, the ADC1xDxxxx(RF)RB Reference Board provides a useful reference design. All design source files for the Reference Board as well as the CAD/CAE symbols for the ADC are available on the product web page or TI-Designs for download. For the purpose of this document, ADC or GSPS ADC refers to the ADC12D1800RF, ADC12D1600RF, ADC12D1000RF, ADC12D800RF, ADC12D500RF, ADC12D1800, ADC12D1600, ADC12D1000, ADC10D1500, ADC10D1000, ADC12D1600QML, and ADC10D1000QML.
Clocking Solution Reference Design for GSPS ADCs
TIDA-00359: Low cost, high performance clocking solution for GSPS data converters. This reference design discusses the use of a TRF3765, a low noise frequency synthesizer, generating the sampling clock for a 4 GSPS analog-to-digital converter (ADC12J4000). Experiments demonstrate data sheet comparable SNR and SFDR performance.
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