BAT54SWT1G中文资料_PDF数据手册

BAT54SWT1G

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0.2A, 30V, 2 ELEMENT, SILICON, SIGNAL DIODE, SOT-323, 3 PIN

技术详情

价格 & 库存

详细参数

不含铅

Active

SC-70

SOT-323, 3 PIN

SOT323

unknown

12782

7.09

SILICON

RECTIFIER DIODE

R-PDSO-G3

0.2 A

PLASTIC/EPOXY

RECTANGULAR

SMALL OUTLINE

260

0.232 W

COMMERCIAL

30 V

0.005 µs

YES

SCHOTTKY

MATTE TIN

GULL WING

DUAL

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BAT54SWT1G Fairchild Semiconductor Corporation 也适用于 BAT54SWT1G BAT54SWT1G ON Semiconductor 也适用于 BAT54SW ,BAT54SWT1 ,NSVBAT54SWT1G 等其余

参考设计

(4)

18-36VDCin, 5V/4A Active Clamp Reference Design

PMP10871: The PMP10871 reference design uses the UCC2897A to control an active clamp forward and converts an 18-36V input to an isolated 5V/4A output with efficiency over 92%. This compact design uses only surface mount components.

Class 4- High Efficiency 12V Class 4 PoE Converter Reference Design

PMP8812: This design is a 12V/2.1A synchronous flyback converter for high efficiency PoE applications. The TPS23752 combines the Powered Device and PWM controllers in one package. Additional features are synchronous rectifier disable for improved light load efficiency and support for ulta low power sleep mode.

Class 3- 36V-72V Input 2.5V/5A Active Clamp Forward; 1/16 Brick

PMP6886: The PMP6886 reference design provides 2.5V at 5A from a standard 48V telecom input with greater than 88% efficiency. This design uses the UCC2897A active clamp controller along with TI NexFET synchronous rectifiers. The low gate thresholds of the CSD16323Q3 and CSD16406Q3 allow them to be driven directly from the transformer windings. The circuit is built in an industry standard 1/16 brick footprint. Auxilliary features of this design include remote sense, output over-voltage protection, output voltage trim and primary side enable control.

Active Clamp Forward Quarter Brick (18 to 60Vdc Input 3.3V/12A) Reference Design

PMP8790: This reference design generates a 3.3V/12A output from a wide 18V-60V telecom input. The UCC2897A controls an active clamp forward converter power stage. The low gate charge and low RDSon of the CSD17501Q5A and CSD18502Q5B, implemented as self-driven synchronous rectifiers, provide for an efficient design. This design is laid out in a standard quarter brick footprint and includes enable, positive rail remote sense, and output trimming features.

< / 共 4 个参考设计 >

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