参考设计
(18)
10/100 Mbps Industrial Ethernet Brick with IEEE 1588 Precision Time Protocol (PTP) Transceiver
TIDA-00496: The TIDA-00496 TI Design is a compact brick for demonstrating capabilities of Precision PHYTERTM. As more systems in the power grid are using time information for real time analysis, timing becomes critical. This design achieves time synchronization with nanosecond accuracy using IEEE 1588v2 Precision Time Protocol (PTP). It can be configured for 10/100 Mbps copper interface or 100 Mbps fiber interface with small form factor LC type transceiver.
TIDEP0054 Parallel Redundancy Protocol (PRP) Ethernet Reference Design for Substation Automation | TI.com
TIDEP0054: This TI Design implements a solution for high-reliability, low-latency network communications for substation automation equipment in Smart Grid transmission and distribution networks. It supports the Parallel Redundancy Protocol (PRP) specification in the IEC 62439 standard using the PRU-ICSS. This solution is a lower-cost alternative to FPGA approaches and provides the flexibility and performance to add features such as IEC 61850 support without additional components.
TIDA-00207 EN55011 Compliant, Industrial Temperature, 10/100Mbps Ethernet PHY Brick Reference Design | TI.com
TIDA-00207: This Ethernet PHY Brick reference design enables Texas Instruments customers to quickly design systems and release them to market, using TI industrial Ethernet PHY transceiver devices, fully compliant to EN5501 Class A EMI requirements. A 50 Pin Interface has been provided to interface with 32-Bit Cortex M4 processor based Controller board. The board has been designed in a small form factor (2 inches x 3 inches) which makes it easy to fit into existing products. This reference design demonstrates the advanced performance of the DP83848K Ethernet PHY transceiver devices, supports 10/100 Base-T and is compliant with IEEE 802.3 standard. The entire reference design operates from a single power supply (5V with On-Board regulator or 3.3V). All other voltages required for the Ethernet PHY transceiver are internally generated.
TIDEP0079 EtherCAT® Master Reference Design on Sitara AM57x Gb Ethernet and PRU-ICSS with Time Triggered Send | TI.com
TIDEP0079: The TIDEP0079 reference design demonstrates an EtherCAT® master interface running on the Sitara™ AM572x processor using the EC-Master stack from acontis. This EtherCAT master solution can be used for EtherCAT-based PLC or motion control applications. EtherCAT master is profiled on both the Ethernet switch and the PRU-ICSS Ethernet ports of the AM572x processor to give designers flexibility to use any of the two switch ports or four PRU-ICSS Ethernet ports on the device. The EtherCAT master implementation can achieve less than 100µs cycle times for both the switch and the PRU-ICSS Ethernet ports. Time-triggered send (TTS) can be enabled on the PRU-ICSS to reduce jitter, achieve shorter cycle times, and reduce latency in cases where distributed clocking is not used.
TIDEP0050 EnDat 2.2 System Reference Design | TI.com
TIDEP0050: The TIDEP0050 TI Design implements the EnDat 2.2 Master protocol stack and hardware interface solution based on the HEIDENHAIN EnDat 2.2 standard for position or rotary encoders. The design is composed of the EnDat 2.2 Master protocol stack, half-duplex communications using RS485 transceivers and the line termination implemented on the Sitara AM437x Industrial Development Kit. This design is fully tested to meet the HEIDENHAIN EnDat 2.2 standard. Along with EnDat position feedback, the AM437x IDK is also able to support industrial communications and motor drive as described in the AM437x Single-Chip Motor-Control Design Guide.
TIDEP0043 Acontis EtherCAT Master Stack Reference Design | TI.com
TIDEP0043: The acontis EC-Master EtherCAT Master stack is a highly portable software stack that can be used on various embedded platforms. The EC-Master supports the high performance TI Sitara MPUs, it provides a sophisticated EtherCAT Master solution which customers can use to implement EtherCAT communication interface boards, EtherCAT based PLC or motion control applications. The EC-Master architectural design does not require additional tasks to be scheduled, thus the full stack functionality is available even on an OS less platform such as TI Starterware suported on AM335x. Due to this architecture combined with the high speed Ethernet driver it is possible to implement EtherCAT master based applications on the Sitara platform with short cycle times of 100 microseconds or even below.
TIDA-00928 EMI/EMC Compliant 10/100 Mbps Ethernet Brick with Fiber or Twisted Pair Interface Reference Design | TI.com
TIDA-00928: This ethernet brick reference design provides a simplified solution that eliminates the need to have multiple boards for copper or fiber interface. It uses a small form factor, low power 10/100 Mbps ethernet transceiver to reduce board size for a cost optimized and scalable solution with reduced power consumption in high temperature industrial applications. The DP83822 provides all physical layer functions needed to transmit and receive data over both standard twisted-pair cables or connect to an external fiber optic (SC or ST or SFP) transceiver. The design provides option to configure different power supply levels for Analog and IO supply using fixed or programmable LDOs. The brick is interfaced to TM4C129X TIVA™ MCU with internal MAC. The design is tested for radiated emission, ESD and EFT as per IEC61000-4 standard level 4.
EN55011 Compliant, Industrial Temperature, 10/100Mbps Ethernet PHY Brick Reference Design
TIDA-00207: This Ethernet PHY Brick reference design enables Texas Instruments customers to quickly design systems and release them to market, using TI industrial Ethernet PHY transceiver devices, fully compliant to EN5501 Class A EMI requirements. A 50 Pin Interface has been provided to interface with 32-Bit Cortex M4 processor based Controller board. The board has been designed in a small form factor (2 inches x 3 inches) which makes it easy to fit into existing products. This reference design demonstrates the advanced performance of the DP83848K Ethernet PHY transceiver devices, supports 10/100 Base-T and is compliant with IEEE 802.3 standard. The entire reference design operates from a single power supply (5V with On-Board regulator or 3.3V). All other voltages required for the Ethernet PHY transceiver are internally generated.
TIDEP0025 Single Chip Drive for Industrial Communications and Motor Control | TI.com
TIDEP0025: This TI design implements a hardware interface solution based on the HEIDENHAIN EnDat 2.2 standard for position or rotary encoders. The platform also allows designers to implement real-time EtherCAT communications standards in a broad range of industrial automation equipment. It enables designers with a low foot print, low power and single chip solution in applications such as industrial automation, factory automation or industrial communication.
Single Chip Drive for Industrial Communications and Motor Control
TIDEP0025: This TI design implements a hardware interface solution based on the HEIDENHAIN EnDat 2.2 standard for position or rotary encoders. The platform also allows designers to implement real-time EtherCAT communications standards in a broad range of industrial automation equipment. It enables designers with a low foot print, low power and single chip solution in applications such as industrial automation, factory automation or industrial communication.
TIDA-00496 10/100 Mbps Industrial Ethernet Brick with IEEE 1588 Precision Time Protocol (PTP) Transceiver | TI.com
TIDA-00496: The TIDA-00496 TI Design is a compact brick for demonstrating capabilities of Precision PHYTERTM. As more systems in the power grid are using time information for real time analysis, timing becomes critical. This design achieves time synchronization with nanosecond accuracy using IEEE 1588v2 Precision Time Protocol (PTP). It can be configured for 10/100 Mbps copper interface or 100 Mbps fiber interface with small form factor LC type transceiver.
EnDat 2.2 System Reference Design
TIDEP0050: The TIDEP0050 TI Design implements the EnDat 2.2 Master protocol stack and hardware interface solution based on the HEIDENHAIN EnDat 2.2 standard for position or rotary encoders. The design is composed of the EnDat 2.2 Master protocol stack, half-duplex communications using RS485 transceivers and the line termination implemented on the Sitara AM437x Industrial Development Kit. This design is fully tested to meet the HEIDENHAIN EnDat 2.2 standard. Along with EnDat position feedback, the AM437x IDK is also able to support industrial communications and motor drive as described in the AM437x Single-Chip Motor-Control Design Guide.
Acontis EtherCAT Master Stack Reference Design
TIDEP0043: The acontis EC-Master EtherCAT Master stack is a highly portable software stack that can be used on various embedded platforms. The EC-Master supports the high performane TI Sitara MPUs, it provides a sophisticated EtherCAT Master solution which customers can use to implement EtherCAT communication interface boards, EtherCAT based PLC or motion control applications. The EC-Master architectural design does not require additional tasks to be scheduled, thus the full stack functionality is available even on an OS less platform such as TI Starterware suported on AM335x. Due to this architecture combined with the high speed Ethernet driver it is possible to implement EtherCAT master based applications on the Sitara platform with short cycle times of 100 microseconds or even below.
TIDEP0078 OPC UA Data Access Server for AM572x Reference Design | TI.com
TIDEP0078: OPC UA is an industrial machine-to-machine protocol designed to allow interoperability and communication between all machines connected under Industry 4.0. The TIDEP0078 TI Design demonstrates use of the MatrikonOPC™ OPC UA server development kit (SDK) to allow communications using an OPC UA data access (DA) server running embedded in a project or design. The OPC UA DA deals with real-time data and is best suited for industrial automation applications where time is an important aspect of the data. A reference OPC UA server implementation is provided that accesses the GPIO capabilities of the AM572x IDK. The reference code can be extended to provide an OPC UA interface to any data the AM572x IDK board can access including data acquired through Profibus, RS-485, CAN bus, and industrial Ethernet-based protocols such as EtherCAT™ or PROFINET™ using the Programmable Real-time Unit Industrial Communication Subsystems (PRU-ICSS).
TIDEP0074 Packet Processing Engine Reference Design for IEC61850 GOOSE Forwarding | TI.com
TIDEP0074: The TIDEP0074 reference design demonstrates packet switching and filtering logic implemented in the M4 core of AM572x based upon the Ethertype, MAC address and Application ID (APPID) of GOOSE packets received from the PRU-ICSS. Packets are filtered and routed to destinations in order to allow the time-critical events defined in substation communication standard IEC 61580 to be serviced in a dedicated core. The design additionally shows multi-core communication between the ARM Cortex™-A15, Cortex™-M4 and DSP C66x™ cores of the AM572x while Linux runs on the A15s and TI-RTOS runs on the M4 and DSP cores.
