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ERJ-3EKF1001V

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ERJ-3EKF1001V
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模型信息提供方: Samacsys
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    参考设计

    (11)
    Ethernet Bootloader for Microcontroller
    TIDM-ETHERNET-BOOTLOADER: This design describes how to use Ethernet module to transfer the firmware image and program it into flash on Hercules MCU. The Ethernet bootloader is based on TFTP (Trivial File Transfer Protocol) which is a file transfer protocol notable for its simplicity. And it is a small piece of code that can be programmed at the beginning of the flash to act as an application loader as well as an update mechanism for applications running on a Hercules microcontroller.
    Altera Arria V GX FPGA Power Solution Reference Design
    PMP9449: The PMP9449 reference design provides all the power supply rails necessary to power Altera's Arria® V GX family of FPGAs. It utilizes a TPS38600 to monitor the input supply and provide power on sequencing. This design features low cost, small footprint discrete ICs and is powered from a single 5V input.
    Automotive Acoustic Knock Sensor Interface
    TIDA-00152: This TIDA-00152 reference design utilizes a dual-channel, signal processing IC for detection of premature detonation in combustion (gasoline) engines. The heart of this design is the TPIC8101 that serves as an interface between acoustical sensors or accelerometers and automobile engine management systems. Programmable features on this device include the selection of engine knock detection sensitivity, engine resonance frequency, and sampling rate control of on-board ADC and DAC in signal processing chain. These features allow the TPIC8101 to be a flexible interface that can adapt to cost and/or processing time constraints of the customer.
    Basestation Transceiver with DPD Feedback Path
    TIDA-00068: The design is for a small cell base station development platform. It provides two real receive paths, two complex transmit paths, and a shared real feedback path. This design has macro basestation performance, but with small cell base station footprint. The current design handles up to 20MHz of bandwidth.
    Wide Bandwidth Optical Front-end Reference Design
    TIDA-00725: This reference design implements and measures a complete 120MHz wide bandwidth optical front end comprising a high speed transimpedance amplifier, fully differential amplifier, and high speed 14-bit 160MSPS ADC with JESD204B interface. Hardware and software are provided to evaluate the performance of the system in response to high speed optical pulses generated from the included laser driver and diode for applications including optical time domain reflectrometry (OTDR).
    Power-optimized 16-bit 1MSPS Data Acquisition Block for Lowest Distortion and Noise Reference Design
    TIPD149: This TI Verified Design is the realization of a high precision, 16-bit 1MSPS data acquisition system suitable for applications such as digital audio that require front-ends with very low distortion and noise. The circuit uses a high performance Successive Approximation Register Analog to Digital Converter (SAR ADC) and has been optimized to provide superior dynamic performance, without excessive power consumption.
    Isolated IGBT Gate Driver Evaluation Platform for 3-Phase Inverter System Reference Design
    TIDA-00195: The TIDA-00195 reference design consists of a 22kW power stage with TI’s new reinforced isolated IGBT gate driver ISO5852S intended for motor control in various applications. This design allows performance evaluation of the ISO5852S in 3-phase inverter incorporating 1200V rated IGBT modules of current ratings ranging from 50A-200A. Some of the important functionality and performance evaluated are short circuit protection using DESAT detection, Soft-shutdown, effectiveness of the Active Miller Clamp at different inverter dv/dt, and ESD/EFT performance of IGBT gate driver at system level derived from adjustable speed electrical power drive systems (IEC61800-3). Piccolo launch pad LAUNCHXL-F28027 is used to generate the PWM signals required for controlling the inverter.
    16-bit 400KSPS 4-Ch. Multiplexed Data Acquisition Ref Design for High Voltage Inputs, Low Distortion
    TIPD151: This TI Verified Design implements a 16-bit, differential 4-channel multiplexed data acquisition system at 400KSPS throughput for high voltage differential input of ±20 V (40 Vpk-pk) industrial applications. The circuit is realized with a 16-bit successive-approximation-resistor (SAR) analog-to-digital converter (ADC), a precision high voltage signal conditioning front end, and a 4-channel differential multiplexer (MUX). The design details the process for optimizing the precision high voltage front end drive circuit using the OPA192 and OPA140 to achieve excellent dynamic performance with the ADS8864.
    Tone Stack for Guitar Amplifier Reference Design
    TIPD186: This split-supply, high-performance guitar tone circuit provides control of the bass, mid, and treble frequencies of an electric guitar signal, while also providing gain with minimal distortion and noise. Buffered inputs and outputs preserve the behavior of the system independent of the source and load impedances, and a radio frequency (RF) filter on the circuit front end attenuates noise from outside the audio band.
    Synchronizing Multiple JESD204B ADCs for Emitter Position Location Reference Design
    TIDA-00467: A common technique to estimate the position of emitters uses the amplitude and phase shift data of a signal derived from an array of spatially distributed sensors. For such systems, it is important to guarantee a deterministic phase relationship between the sensors to minimize errors in the actual measured data. This application design will discuss how multiple Analog to Digital Converters (ADCs) with a JESD204B interface can be synchronized so that the sampled data from the ADCs are phase aligned.
    Direct Down-Conversion System with I/Q Correction
    TIDA-00078: The I/Q Correction block implemented in the Field Programmable Gate Array (FPGA) of the TSW6011EVM helps users to adopt a direct down conversion receiver architecture in a wireless system. The I/Q correction block consists of a single-tap blind algorithm, which corrects the frequency-independent I/Q imbalance in a complex zero-IF receiver system. Along with the I/Q correction block, the FPGA includes a digital gain block, a digital power-measurement block, x2 of interpolation block, an I/Q offset correction block, and a quadrature mixing block.
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