参考设计
(22)
Xilinx® Zynq® 7000 series (XC7Z015) Power Solution, 8W - Reference Design
PMP10601.1: The PMP10601 reference design provides all the power supply rails necessary to power Xilinx® Zynq® 7000 series (XC7Z015) FPGA. This design uses several LMZ3 series modules, LDOs, and a DDR termination regulator to provide all the necessary rails to power the FPGA. It also features one LM3880 for power up and power down sequencing. This design uses a 12V input.
12Vin, 1.2V/1.7A Low Cost, Small Form Factor, Synchronous Buck Reference Design
PMP9726: This reference design generates a 1.2V output from a 12V input, using the TPS562209 synchronous buck converter. This converter uses the DCAP2 control method to minimize output capacitance while eliminating feedback compensation components and still providing an excellent load transient response. The converter switches at 650kHz. The peak efficiency of this design is 83%.
Xilinx® Zynq® 7000 series (XC7Z015) Power Solution, 8W - Reference Design
PMP10601.2: The PMP10601 reference design provides all the power supply rails necessary to power Xilinx® Zynq® 7000 series (XC7Z015) FPGA. This design uses several LMZ3 series modules, LDOs, and a DDR termination regulator to provide all the necessary rails to power the FPGA. It also features one LM3880 for power up and power down sequencing. This design uses a 12V input.
High Efficiency 400W AC/DC Power Supply Reference Design - PMP11064.1 - TI Tool Folder
PMP11064: PMP11064 is a high-efficiency AC/DC power supply reference design with universal AC input and 20V/20A output. Interleaved transition mode PFC and LLC series resonant converter is applied for 20V/20A main power. A PSR Flyback with MOSFET integrated controller is applied as the auxiliary supply. 91.2% efficiency is achieved at low line and full load. 93.1% efficiency is achieved at high line and full load.
Xilinx(r) Ultrascale(r) 16nm FPGA/SoC Power Solution for Mobile Radio Basestation with PMBus
PMP10555: The PMP10555 reference design provides all the power supply rails necessary to power Xilinx® Ultrascale® 16nm family of FPGAs/SoCs in a mobile radio basestation application. This design uses a PMBus compatible 20A integrated FET buck converter for the core and two multi-output buck regulator ICs to provide the remaining supplies necessary rails to power the FPGA. It also features two LM3880's for flexible power up and power down sequencing. This design uses a 12V input.
Wide Bandwidth Optical Front-end Reference Design
TIDA-00725: This reference design implements and measures a complete 120MHz wide bandwidth optical front end comprising a high speed transimpedance amplifier, fully differential amplifier, and high speed 14-bit 160MSPS ADC with JESD204B interface. Hardware and software are provided to evaluate the performance of the system in response to high speed optical pulses generated from the included laser driver and diode for applications including optical time domain reflectrometry (OTDR).
Xilinx Kintex UltraScale FPGA Power Solution Reference Design with PMBus
PMP9444: The PMP9444 reference design provides all the power supply rails necessary to power Xilinx's Kintex UltraScale family of FPGAs. It features two UCD90120A's for flexible power up and power down sequencing as well as voltage monitoring, current monitoring, and voltage margining through the PMBus interface. This design uses a 12V input.
Xilinx® Zynq®7000 series (XC7Z015) Power Solution, 5W - Reference Design
PMP10600.2: The PMP10600.2 reference design provides all the power supply rails necessary to power Xilinx® Zynq® 7000 series (XC7Z015) FPGA. This design uses several LMZ3 series modules, LDOs, and a DDR termination regulator. It also features one LM3880 for power up and power down sequencing. This design uses a 12V input.
Xilinx Virtex Ultrascale FPGA Multi-Gigabit Transceiver (MGT) Power Reference Design with PMBus
PMP9407: The PMP9407 reference design provides all the power supply rails necessary to power the multi-gigabit transcievers (MGT) in Xilinx's Virtex® Ultrascale™ FPGAs. This design uses a 5V input and has a PMBus interface for current and voltage monitoring, margining, timing delays, and fault monitoring. It uses two TPS544B20's which feature internal current sensing and eliminate the need for an external current sense resistor. This design also meets Xilinx's low output voltage ripple requirements of the MGT rails.
18Vdc-60Vdc Input, 3.3V/15A Active Clamp Forward, 1/8 Brick Reference Design
PMP8973: The PMP8973 reference design generates a 3.3V/15A output from an 18V to 60V telecom input. The UCC2897A controls an active clamp forward converter power stage. The low gate charge and low RDSon of the CSD16415Q5 and CSD18502Q5B, implemented as synchronous rectifiers, provides for a highly efficient design. This design is laid out in a standard eighth brick footprint and achieves peak efficiencies over 92%. It includes remote sensing of the output voltage.
Xilinx Zynq 7000 Series (XC7Z045) 20W Reference Design
PMP10613.2: The PMP10613 reference design provides all the power supply rails necessary to power Xilinx® Zynq® 7000 series (XC7Z045) FPGA. This design uses several LMZ3 series modules, LDOs, and a DDR termination regulator to provide all the necessary rails to power the FPGA. It also features one LM3880 for power up and power down sequencing. This design uses a 12V input.
12Vin, 3.3V/1.7A Low Cost, Small Form Factor, Synchronous Buck Reference Design
PMP9725: The PMP9725 reference design generates a 3.3V output from a 12V input, using the TPS562209 synchronous buck converter. This converter uses the DCAP2 control method to minimize output capacitance while eliminating feedback compensation components and still providing an excellent load transient response. The converter switches at 650kHz. The peak efficiency of this design is 90%.
Xilinx Zynq 7000 Series (XC7Z045) 20W Reference Design
PMP10613.1: The PMP10613 reference design provides all the power supply rails necessary to power Xilinx® Zynq® 7000 series (XC7Z045) FPGA. This design uses several LMZ3 series modules, LDOs, and a DDR termination regulator to provide all the necessary rails to power the FPGA. It also features one LM3880 for power up and power down sequencing. This design uses a 12V input.
High Density 4A DC-DC Buck Converter with PMBus Interface Reference Design
PMP11140: The PMP11140 reference design shows 1.8V 4A (3A without fan) for CPU I/O and other applications in a 22 cm by 12.5 cm single sided footprint. Control allows external synchronization to allow improved management of system noise. A rich Test Interface is provided including an on board dynamic load.
Xilinx® Zynq®7000 series (XC7Z015) Power Solution, 5W - Reference Design
PMP10600.1: The PMP10600.1 reference design provides all the power supply rails necessary to power Xilinx® Zynq® 7000 series (XC7Z015) FPGA. This design uses several LMZ3 series modules, LDOs, and a DDR termination regulator. It also features one LM3880 for power up and power down sequencing. This design uses a 12V input.
Xilinx Zynq 7000 Series (XC7Z045) 20W Reference Design - PMP10613.1 - TI Tool Folder
PMP10613: The PMP10613 reference design provides all the power supply rails necessary to power Xilinx® Zynq® 7000 series (XC7Z045) FPGA. This design uses several LMZ3 series modules, LDOs, and a DDR termination regulator to provide all the necessary rails to power the FPGA. It also features one LM3880 for power up and power down sequencing. This design uses a 12V input.
Xilinx Virtex UltraScale FPGA Power Solution with PMBus Reference Design
PMP9475: The PMP9475 12V-input reference design provides all the power supply rails necessary to power Xilinx's Virtex® UltraScale™ family of FPGAs in a compact, highly efficient design. This design uses several of TI's PMBus Point-Of-Load voltage regulators for ease of design/configuration and telemetry of critical rails. It features a UCD90120A for flexible power up and power down sequencing as well as voltage monitoring, current monitoring, and voltage margining through the PMBus interface.
