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首页 > 电子元器件选型 > 信号电路 > 锁相环或频率合成电路

LMX2581SQX/NOPB

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LMX2581SQX/NOPB
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Texas Instruments

3.76-GHz wideband frequency synthesizer with integrated VCO 32-WQFN -40 to 85

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TIDA-00426 12-Gbps Multi-Channel BERT Board Reference Design | TI.com
TIDA-00426: This reference design is a 12-Gbps low-cost bit error tester (BERT) capable of generating and checking up to 8 channels of pseudo-random binary sequences (PRBS). This validated design is a convenient way to generate multi-channels high speed serial bit streams of up to 12-Gbps, and checking incoming serial bit streams for possble bit errors. This design can be used as a hand-held BERT useful for evaluating the signal integrity and bit error error performance of a high speed sub-system.
TIDA-00360 700–2700 MHz Dual-Channel Receiver with 16-Bit ADC and 100 MHz IF Bandwidth Reference Design | TI.com
TIDA-00360: The increasing demand on wireless networks to provide faster data links to customers has driven transceiver hardware to increasingly demanding performance with enough bandwidth to support the largest standardized multi-carrier frequency bands (with band aggregation in some cases) and enough receiver sensitivity and dynamic range to function in the presence of the strong blocking signals common in busy environments. This TI Design describes a RF receiver subsystem reference design with 16-bit sampler that achieves more than 100MHz of bandwidth including a down-converting mixer, digital variable gain amplifier (DVGA), high speed pipelined analog-to-digital converter (ADC), local oscillator (LO) RF synthesizer, and jitter-cleaning clock generator.
700–2700 MHz Dual-Channel Receiver with 16-Bit ADC and 100 MHz IF Bandwidth Reference Design
TIDA-00360: The increasing demand on wireless networks to provide faster data links to customers has driven transceiver hardware to increasingly demanding performance with enough bandwidth to support the largest standardized multi-carrier frequency bands (with band aggregation in some cases) and enough receiver sensitivity and dynamic range to function in the presence of the strong blocking signals common in busy environments. This TI Design describes a RF receiver subsystem reference design with 16-bit sampler that achieves more than 100MHz of bandwidth including a down-converting mixer, digital variable gain amplifier (DVGA), high speed pipelined analog-to-digital converter (ADC), local oscillator (LO) RF synthesizer, and jitter-cleaning clock generator.
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