SN74LVC244ARWPR中文资料_PDF数据手册

SN74LVC244ARWPR

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Texas Instruments

8-ch, 1.65-V to 3.6-V buffers with 3-state outputs 20-X1QFN -40 to 125

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详细参数

Source Content uid

SN74LVC244ARWPR

Brand Name

Texas Instruments

不含铅

符合

Active

X1QFN-20

compliant

EAR99

8542.39.00.01

Date Of Intro

2016-05-28

478

1.5

LVC/LCX/Z

R-PQCC-N20

3.3 mm

BUS DRIVER

0.024 A

125 °C

-40 °C

3-STATE

TRUE

PLASTIC/EPOXY

HVQCCN

RECTANGULAR

260

0.04 mA

16.4 ns

0.5 mm

3.6 V

1.65 V

1.8 V

YES

CMOS

AUTOMOTIVE

NICKEL PALLADIUM GOLD

NO LEAD

0.4 mm

QUAD

2.5 mm

参考设计

(3)

TIDA-01233 Ultra-Small, Flexible LED Expansion Reference Design | TI.com

TIDA-01233: This document focuses on two reference designs using the SN74HC595B 8-bit Shift Register with 3-State Output Registers and the SN74LVC244A Octal Buffer with 3-State Outputs, each used to expand three general purpose outputs on a microcontroller to eight or more general purpose outputs. Both devices are available in the ultra-small X2SON package. The Seven Segment Driver Reference Design focuses on individually controlling the eight LEDs in seven-segments with hardware that fits underneath the display module. This 8×8 LED Matrix Reference Design focuses on driving 64 LEDs arranged as an 8×8 matrix display that could be panelized to create larger displays.

TIDEP0056 Thermal Printing with the PRU-ICSS on the BeagleBone Black Reference Design | TI.com

TIDEP0056: The Programmable Realtime Unit – Industrial Communications Sub-System (PRU-ICSS) is a versatile component of the AM335x SoC that enables real-time, deterministic, fast GPIO control, even when running a non-deterministic operating system. This reference design provides a concrete use case and implementation of the PRU-ICSS to directly control a thermal printer module. Included are C code examples for ARM to PRU communications, real-time GPIO pin control to drive the thermal print head elements and stepper motors, and pinmux configuration.

TIDEP0081 Wideband Receiver Design Using 66AK2L06 JESD204B Attach to ADC32RF80 Reference Design | TI.com

TIDEP0081: For wideband receiver system developers currently using FPGA or ASIC to connect High Speed data converters to a baseband processor, who need faster time to market with increased performance and significant reduction in cost, power, and size. This reference design includes the first widely available processor integrating a JESD204B interface and Digital Front End Processing (DFE). Connecting ADC32RF80 to DAC38J84 provides an efficient solution for avionics and defense, test and measurements and industrial applications.

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